26.1 Block Transfer Control

Table 26-4. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: BTCTRL
Offset: 0x00
Reset: 0x0000
Property: RW

Bit 15141312111098 
 STEPSIZE[2:0]STEPSELDSTINCSRCINCBEATSIZE[1:0] 
Access  
Reset 00000000 
Bit 76543210 
    BLOCKACT[1:0]EVOSEL[1:0]VALID 
Access  
Reset 00000 

Bits 15:13 – STEPSIZE[2:0] Address Increment Step Size

ValueNameDescription
0x0X1Next ADDR = ADDR + (BEATSIZE+1) * 1
0x1X2Next ADDR = ADDR + (BEATSIZE+1) * 2
0x2X4Next ADDR = ADDR + (BEATSIZE+1) * 4
0x3X8Next ADDR = ADDR + (BEATSIZE+1) * 8
0x4X16Next ADDR = ADDR + (BEATSIZE+1) * 16
0x5X32Next ADDR = ADDR + (BEATSIZE+1) * 32
0x6X64Next ADDR = ADDR + (BEATSIZE+1) * 64
0x7X128Next ADDR = ADDR + (BEATSIZE+1) * 128

Bit 12 – STEPSEL Step Selection

ValueNameDescription
0x0DSTStep size settings apply to the destination address
0x1SRCStep size settings apply to the source address

Bit 11 – DSTINC Destination Address Increment Enable

Bit 10 – SRCINC Source Address Increment Enable

Bits 9:8 – BEATSIZE[1:0] Beat Size

ValueNameDescription
0x0BYTE8-bit bus transfer
0x1HWORD16-bit bus transfer
0x2WORD32-bit bus transfer

Bits 4:3 – BLOCKACT[1:0] Block Action

ValueNameDescription
0x0NOACTChannel will be disabled if it is the last block transfer in the transaction
0x1INTChannel will be disabled if it is the last block transfer in the transaction and block interrupt
0x2SUSPENDChannel suspend operation is completed
0x3BOTHBoth channel suspend operation and block interrupt

Bits 2:1 – EVOSEL[1:0] Event Output Selection

ValueNameDescription
0x0DISABLEEvent generation disabled
0x1BLOCKEvent strobe when block transfer complete
0x3BEATEvent strobe when beat transfer complete

Bit 0 – VALID Descriptor Valid