21.4.2.2 Selecting the Synchronous Clock Division Ratio

Each CLKDIVx.DIV divider can be changed on the fly without halting or disabling the peripheral modules connected to it. This change allows responding to variable load in the application and is applied to all synchronous clocks belonging to the corresponding clock domain at the same time.

To ensure correct operation:

• Frequencies must be selected so that fCD0 ≥ fCD1 ≥ fCD2. Values that violates this relationship will be discarded and will generate a bus error, logged in the PAC module.
• Frequencies must never exceed the specified maximum frequency for each clock domain given in the electrical characteristics specifications.
• Wait for INTFLAG.CLKRDY = 1, change CLKDIVx.DIV, and wait for CLKRDY to come back to 1.