21.4.2.4 Peripheral Clock Masking

All synchronous clocks can then be masked/unmasked individually by writing the corresponding bit in the Clock Mask registers (CLKMSKx.MASKy), where the x and y indexes are defined in the Peripherals Configuration Summary.

All synchronous clocks are unmasked by default after reset.

When a peripheral clock is unmasked and the peripheral is:

• Not enabled (CTRLA.ENABLE = 0), then the clock is automatically gated at the MCLK output to save power consumption, and automatically ungated when read/write register accesses are made in this peripheral
• Enabled (CTRLA.ENABLE = 1), the clock is permanently requested and delivered

When a peripheral clock is masked, its synchronous clock is gated at the MCLK level, saving power consumption in the clock tree, but making the peripheral registers no more accessible. Read/write accesses to the peripheral registers will fail and return an error.

Clocks should only be switched off if it is certain that the module will not be used: Switching off the clock for the NVM Controller (NVMCTRL) will cause a problem if the CPU needs to read from the Flash Memory. Switching off the clock to the MCLK module (which contains the mask registers) or the APB0 bridge, will make it impossible to write the mask registers again. In this case, they can only be re-enabled by a system reset.

A module may be connected to several clock domains (for instance, AHB and APB), in which case it will have several mask bits.

The CPU clock to the Arm Cortex processor is derived from the clock domains 0 and runs at fCD0. It is controlled automatically and does not depend on a CLKMSKx.MASK bit.