1.3 Motorola SPI Protocol
Motorola SPI Mode 3 is required to communicate with SmartFusion2, IGLOO2, PolarFire, and PolarFire SoC devices using a dedicated system controller SPI port. See Motorola SPI standard for more information.
The Motorola SPI is a full duplex, four-wire synchronous transfer protocol, which supports programmable clock polarity (SPO) and clock phase (SPH). The state of SPO and SPH control bits decides the data transfer modes as listed in the following table.
| Data Transfer Mode | SPO | SPH |
|---|---|---|
| Mode 0 | 0 | 0 |
| Mode 1 | 0 | 1 |
| Mode 2 | 1 | 0 |
| Mode 3 | 1 | 1 |
The SPH control bit determines the clock edge that captures the data.
- When SPH is low, data is captured on the first
clock transition.
- Data is captured on the
falling edge of
SPI_CLKwhen SPO = 1. - Data is captured on the
rising edge of
SPI_CLKwhen SPO = 0.
- Data is captured on the
falling edge of
- When SPH is high, data is captured on
the second clock transition (rising edge if SPO = 1).
- Data is captured on the
rising edge of
SPI_CLKwhen SPO = 1. - Data is captured on the
falling edge of
SPI_CLKwhen SPO = 0.
- Data is captured on the
rising edge of
The SPO control bit determines the polarity of the clock and SPS defines the slave select behavior.
- When SPO is low and no data is transferred,
SPI_CLKis driven to low. - When SPO is high and no data is
transferred,
SPI_CLKis driven to high.
| Mode | SPS | SPO | SPH | Clock in Idle | Sample Edge | Shift Edge | Select in Idle | Select Between Frames |
|---|---|---|---|---|---|---|---|---|
| Motorola | 0 | 0 | 0 | Low | Rising | Falling | High | Pulses between all frames |
| 0 | 1 | 0 | High | Falling | Rising | High | ||
| 0 | 0 | 1 | Low | Falling | Rising | High | Does not pulse between back-to-back frames. Pulses if transmit FIFO empties. | |
| 0 | 1 | 1 | High | Rising | Falling | High | Does not pulse between back-to-back frames. Pulses if transmit FIFO empties. | |
| 1 | 0 | 0 | Low | Rising | Falling | High | Stays active until all the frames set by frame counter are transmitted. | |
| 1 | 0 | 1 | Low | Falling | Rising | High | ||
| 1 | 1 | 0 | High | Falling | Rising | High | ||
| 1 | 1 | 1 | High | Rising | Falling | High |
Single Frame Transfer - Mode 0: SPO = 0, SPH = 0
The following figure illustrates the single frame transfer using Mode 0 data transfer mode with programmable clock polarity 0 and clock phase 0.
Multiple Frame Transfer - Mode 0: SPO = 0, SPH = 0
The following figure illustrates the multiple frame transfer using the Mode 0 data transfer mode with programmable clock polarity 0 and clock phase 0.
Notes:
Between frames, the slave selects (
SPI_SS[x]) a signal that is asserted for the duration of the clock pulse.Between frames, the clock (
SPI_CLK) is low.Data is transferred to Most Significant Bit (MSB) first.
The output enables (
SPI_DOE_N) a signal that is asserted during the transmission and deasserted at the end of the transfer (after the last frame is sent).
Single Frame Transfer - Mode 1: SPO = 0, SPH = 1
The following figure illustrates the single frame transfer using the Mode 1 data transfer mode with programmable clock polarity 0 and clock phase 1.
Single Frame Transfer - Mode 2: SPO = 1, SPH = 0
The following figure illustrates the single frame transfer using the Mode 2 data transfer mode with programmable clock polarity 1 and clock phase 0.
Single Frame Transfer - Mode 3: SPO = 1, SPH = 1
The following figure illustrates the single frame transfer using the Mode 3 data transfer mode with programmable clock polarity 1 and clock phase 1.
