18.2 Mask Values

The mask value of a device Configuration is calculated by setting all the unimplemented bits to ‘0’ and all the implemented bits to ‘1’.

For example, Register 18-1 shows the DEVCFG0 register of the PIC32MX360F512L device. The mask value for this register is as follows:
  • mask_value_devcfg0 = 0x110FF00B

Table 18-1 lists the mask values of the four device Configuration registers and device ID registers to be used in the checksum calculations for the PIC32MX, PIC32MZ and PIC32MKXXXXGPD/GPE/MCFXXX devices. PIC32MKXXXXGPK/MCM/GPG/MCJXXX devices use the CRC32 checksum. For additional information on the CRC32 checksum, refer to the “Checksum Changes” chapter of the document “Readme for MPLABX IDE.htm”, which can be found at <MPLABX Installation Path>\<MPLABX Revision>\docs.

Table 18-1. Device Configuration Register Mask Values Of Currently Supported PIC32MX, PIC32MZ AND PIC32MKXXXXGPD/GPE/MCFXXX Devices
Device FamilyFlash Memory Sizes (KB)DEVCFG0DEVCFG1DEVCFG2DEVCFG3DEVCFG4DEVID
PIC32MX110/120/130/ 150F0xx PIC32MX150F128 (28/36/44-pin devices only)16, 32, 64, 1280x1100FC1F0x03DFF7A70x000700770xF000FFFF0x0FFFFFFF
PIC32MX130F128/256 PIC32MX150F256 (28/36/44-pin devices only)16, 32, 64, 1280x1100FC1F0x03DFF7A70x00070077

0xF0000000

0x0FFFFFFF
PIC32MX210/220/230/ 250 (28/36/44-pin devices only)16, 32, 64, 1280x1100FC1F0x03DFF7A70x000787770xF00000000x0FFFFFFF
PIC32MX15X/17X (28/44-pin devices only)128, 2560x1187F01F0x03FFF7A70xFFB700F70x30C000000x0FFFFFFF
PIC32MX25X/27X (28/44-pin devices only)128, 2560x1187F01F0x03FFF7A70xFFB787F70x70C000000x0FFFFFFF
PIC32MX320/340/36032, 64, 128, 256, 5120x110FF00B0x009FF7A70x000700770x0000FFFF0x000FF000
PIC32MX420/440/46032, 64, 128, 256, 5120x110FF00B0x009FF7A70x000787770x0000FFFF0x000FF000
PIC32MX110/120/130/ 150F0xx PIC32MX150F128 PIC32MX170F256 (64/100-pin devices only)64, 128, 256, 5120x110FFC1F0x03DFF7A70x000700770xF000FFFF0x0FFFFFFF
PIC32MX130F128/256 PIC32MX150F256 PIC32MX170F512 (64/100-pin devices only)64, 128, 256, 5120x110FFC1F0x03DFF7A70x000700770xF00000000x0FFFFFFF
PIC32MX230F0xx PIC32MX250F128 PIC32MX270F256 (64/100-pin devices only)64, 128, 256, 5120x110FFC1F0x03DFF7A70x000787770xF000FFFF0x0FFFFFFF
PIC32MX230F128 PIC32MX230F256 PIC32MX250F256 PIC32MX270F512 PIC32MX530 PIC32MX550 PIC32MX570 (64/100-pin devices only)64, 128, 256, 5120x110FFC1F0x03DFF7A70x000787770xF00000000x0FFFFFFF
PIC32MX330/350/37064, 128, 256, 5120x110FF01F0x03DFF7A70x000700770x3007FFFF0x0FFFFFFF
PIC32MX430/450/47064, 128, 256, 5120x110FF01F0x03DFF7A70x000787770xF007FFFF0x0FFFFFFF
PIC32MX534/56464, 1280x110FF00F0x009FF7A70x000787770xC407FFFF0x0FFFF000
PIC32MX66464, 1280x110FF00F0x009FF7A70x000787770xC307FFFF0x0FFFF000

PIC32MK0512/

1024XXD/E/F

512, 10240x7FFFFFFF0xFFFFFFFF0xFFFFFFFF0xFFFF00000x0FFFFFFF
PIC32MX7641280x110FF00F0x009FF7A70x000787770xC707FFFF0x0FFFF000
PIC32MX170F256 (28/36/44-pin devices only)2560x1107FC1F0x03DFF7A70x000700770xF000FFFF0x0FFFFFFF
PIC32MX170F512 (28/36/44-pin devices only)2560x1107FC1F0x03DFF7A70x000700770xF00000000x0FFFFFFF
PIC32MX270F256 (28/36/44-pin devices only)2560x1107FC1F0x03DFF7A70x000787770xF000FFFF0x0FFFFFFF
PIC32MX270F512 (28/36/44-pin devices only)2560x1107FC1F0x03DFF7A70x000787770xF00000000x0FFFFFFF
PIC32MZ05XX/10XX/20XX512, 1024, 20480x7FFFFFFF0xFFFFFFFF0xFFFFFFFF0xFFFF00000xFFFFFFF(1)0x0FFFFFFF
PIC32MX575256, 5120x110FF00F0x009FF7A70x000787770xC407FFFF0x000FF000
PIC32MX675/695256, 5120x110FF00F0x009FF7A70x000787770xC307FFFF0x000FF000
PIC32MX775/795256, 5120x110FF00F0x009FF7A70x000787770xC707FFFF0x000FF000
PIC32MZW11024, 20480xFFB3FDFD0x1FFFFF3B0xFFFFFF380x0003FFFF0x5FF800FF0xFFFFFFFF
Note:
  1. Applicable only to the PIC32MZ DA family of devices.
  2. Device Configuration register mask values of the PIC32MZ for:
    • USERID: 0x0000FFF
    • BCFG0: 0x8000000B