AN4663

1.4.1.1 PF_CCC_0 Configuration

The PolarFire Clock Conditioning Circuitry (CCC) block takes an input clock of 50 MHz from the onboard oscillator and generates a 83.33 MHz fabric clock to the Mi-V processor subsystem and other peripherals.

The following figures show the input and output clock configurations.

Figure 1-4. PF_CCC_0 Input Clock Configuration

The following figure shows the PF_CCC_0 output clock configuration. This design uses a 83.33 MHz system clock for configuring the APB peripherals.

Figure 1-5. PF_CCC_0 Output Clock Configuration

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