1.4.1.3 MIV ESS Core

The MIV_ESS is a MI-V ecosystem IP core available for the Microchip FPGA and System- on-Chip (SoC) FPGA device families. The core is a multi-featured, highly-configurable, Extended Subsystem (ESS), which supports bothbootstrap and base peripherals. It is specifically designed to use with the MIV_RV32 soft processor. APB interface connects the PF_SYSTEM_SERVICES, CoreSPI as an external peripheral.

Instantiating MiV ESS Core

To instantiate the MiV ESS core, perform the following steps:

  1. From the Catalog, drag the MIV_ESS IP core to Smart Design.
  2. In the Create Component dialog box, enter MIV_ESS_C0 as the component name, and click OK.
  3. In the MiV ESS Configurator screen, perform the following configurations:
    • Navigate to General tab, and make sure that the configurations are same as shown in the following figure.
      Figure 1-8. General Tab
    • Navigate to APB tab, and select APB configuration as shown in the following figure.
      Figure 1-9. APB Tab
    • Navigate to GPIO tab, and make sure that the configurations are same as shown in the following figure.
      Figure 1-10. GPIO Tab
    • Navigate to UART tab, and make sure that the configurations are same as shown in the following figure.
      Figure 1-11. UART Tab

APB module used in the MIV_ESS core. ABP interface is used to connect Base peripherals. The final addresses for PF_SYSTEM_SERVICES, CoreGPIO, and CoreUARTapb targets are translated into 0x6300_0000, 0x6500_0000, and 0x6100_0000 respectively.