40.5.6 DMA Operation
| Instance | Channel | CHCTRLB.TRIGSRC [Index] | Presentation |
|---|---|---|---|
| ADC | PFFRDY | 37 | ADC DMA PFFRDY Trigger |
The DMA can be programmed to read the APB Bus FIFO when there is available data. The register value PFFCTRL.PFFRDYDMA controls whether the DMA will be read when the FIFO is half full (0), or Not Empty (1). CTLINTFLAG.PFFHFUL and CTLINTFLAG.PFFRDY will be set when data is to be read.
For the FIFO to work, first enable the FIFO by setting PFFCTRL.PFFEN = 1. Next enable the ADC Core by setting PFFCTRL.PFFCRk = 1. See the section “ADC Result FIFO” for more information.