40.5.1 Principle of Operation
Important: When AVDD < 2.5V,
it is recommended that the user enable the analog charge pumps when in active mode by
setting the SUPC.VREGCTRL.CPEN[1:0] bits. When the CPEN[N] bits are set, the enable and
auto-enable of the associated charge pump[N] are set.
The basic architecture of an ADC Module is shown in the following figure.
At the start of a capture cycle the Sample and Hold capacitor is connected to the incoming voltage on a trigger event until the expiration of the sample time defined by CORCTRLx.SAMC. At the end of the sampling period the Sample and Hold is disconnected from the input signal and connected to the Comparator and the conversion sequence begins. ADC conversion time = (# bits +1)*TAD).