40.5.12 Register Synchronization

All peripherals are composed of one digital bus interface connected to the APB bus and running from a corresponding clock in the Main Clock (MCLK) domain, and one peripheral core running from the peripheral Generic Clock (GCLK).

Communication between these clock domains must be synchronized. This mechanism is implemented in hardware, so the synchronization process takes place even if the peripheral generic clock is running from the same clock source and on the same frequency as the bus interface.

All registers in the bus interface are accessible without synchronization. All registers in the peripheral core are synchronized when written. Some registers in the peripheral core are synchronized when read.

Each individual register description will have the properties "Read-Synchronized" and/or "Write- Synchronized" if a register is synchronized.

Each register that requires synchronization has its individual synchronizer and its individual synchronization status bit in the Synchronization Busy register (SYNCBUSY).

Note: For registers requiring both read- and write-synchronization, the corresponding bit in SYNCBUSY is shared.

The SYNCBUSY register supports the CTRLA.ENABLE bit and the CTRLB register.

When SYNCBUSY.ENABLE has been set, no additional writes to the CTRLA.ENABLE are allowed.

When SYNCBUSY.CTRLB has been set, no additional writes to the CTRLB register are allowed.

Synchronization:
  • Read-Synchronized registers: Synchronized each time the register value is updated but the corresponding SYNCBUSY bits are not set. Reading a read-synchronized register does not start a new synchronization, it returns the last synchronized value.
  • Write-Synchronized register: Any write access while the SYNCBUSY bit is set will be executed successfully.
Note: The corresponding bits in SYNCBUSY will automatically be set when the device wakes up from sleep because read-synchronized registers need to be synchronized. Therefore reading a read synchronized register before its corresponding SYNCBUSY bit is cleared will return the last synchronized value before sleep mode.

Register synchronization is required for other registers in the GLCK clock domain. These registers can be modified while CTRLA.ENABLE = 0, that is, as long as the ADC is not enabled. Once the ADC is enabled (CTRLA.ENABLE = 1) these registers are synchronized to the APB_CLK (Main Clock) domain and are write protected.