27.9.9 Counter Period in COUNT16 mode
(CTRLA.MODE=1)
Table 27-23. Register Bit Attribute Legend
Symbol
Description
Symbol
Description
Symbol
Description
R
Readable bit
HC
Cleared by Hardware
(Grey cell)
Unimplemented
W
Writable bit
HS
Set by Hardware
X
Bit is unknown at Reset
K
Write to clear
S
Software settable bit
—
—
Note: This register is
write-synchronized: SYNCBUSY.PER must be checked to ensure the PER register
synchronization is complete.
Name:
PER
Offset:
0x1C
Reset:
0x0000
Property:
PAC Write-Protection,
Write-Synchronized
Bit
15
14
13
12
11
10
9
8
PER[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PER[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 15:0 – PER[15:0] Counter Period
These bits define
the value of the 16-bit RTC period in COUNT16 mode
(CTRLA.MODE=1).
DS60001921A
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