27.9.7 Synchronization Busy Status
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | SYNCBUSY |
| Offset: | 0x10 |
| Reset: | 0x00000000 |
| Property: | R |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| GP3 | GP2 | GP1 | GP0 | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| COUNTSYNC | COMP3 | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| COMP2 | COMP1 | COMP0 | PER | COUNT | FREQCORR | ENABLE | SWRST | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 16, 17, 18, 19 – GPn General Purpose n Synchronization Busy Status
| Value | Description |
|---|---|
| 0 | Write synchronization for GPn register is complete. |
| 1 | Write synchronization for GPn register is ongoing. |
Bit 15 – COUNTSYNC Count Synchronization Enable Bit Busy
| Value | Description |
|---|---|
| 0 | Write synchronization for CTRLA.COUNTSYNC bit is complete. |
| 1 | Write synchronization for CTRLA.COUNTSYNC bit is ongoing. |
Bits 5, 6, 7, 8 – COMPn Compare n Synchronization Busy Status [n = 3..0]
| Value | Description |
|---|---|
| 0 | Write synchronization for COMPn register is complete. |
| 1 | Write synchronization for COMPn register is ongoing. |
Bit 4 – PER PER Register Busy
| Value | Description |
|---|---|
| 0 | Write synchronization for PER register is complete. |
| 1 | Write synchronization for PER register is ongoing. |
Bit 3 – COUNT COUNT Register Busy
| Value | Description |
|---|---|
| 0 | Read/write synchronization for COUNT register is complete. |
| 1 | Read/write synchronization for COUNT register is ongoing. |
Bit 2 – FREQCORR FREQCORR Register Busy
| Value | Description |
|---|---|
| 0 | Write synchronization for FREQCORR register is complete. |
| 1 | Write synchronization for FREQCORR register is ongoing. |
Bit 1 – ENABLE Enable Bit Busy
| Value | Description |
|---|---|
| 0 | Write synchronization for CTRLA.ENABLE bit is complete. |
| 1 | Write synchronization for CTRLA.ENABLE bit is ongoing. |
Bit 0 – SWRST Software Reset Bit Busy
| Value | Description |
|---|---|
| 0 | Write synchronization for CTRLA.SWRST bit is complete. |
| 1 | Write synchronization for CTRLA.SWRST bit is ongoing. |