33.2.4.1 Read Control Overview

The FCR provides read access to the Flash system for the CPU and peripheral hosts. It implements 1 AHB client. This interface runs at the same frequency as the system bus and uses the same Flash access timing control.

AHB interface 1 supports a prefetch buffer and cache (PCACHE). The size of the cache is 128 by 4 lines. The PCACHE is unified and treats instructions and data the same. The predictive prefetch unit hides the access time of the Flash memory by fetching the instructions from the next sequential address while the prior instructions are being fetched and executed.

Accesses that hit the cache or prefetch buffer are returned with zero wait states. Misses access the Flash and therefore act according to FWS[3:0] - Flash Access Time Wait States (Defined in terms of AHB Clocks).