33.2.4.2 CTRLA SFR Description
The CTRLA fields can be changed at anytime, provided the FCR is not write protected. New wait state values are used on the next Flash read. RDBUFWS changes are used on the next update to the associated read buffer. A new arbitration value is used at the next available arbitration cycle on a per panel basis.
The register values for CTRLA are given below.
PRIV - Privileged Access Only
The PRIV field determines if the FCR module accepts all accesses or only privileged accesses. It is set to privileged (1) by default.
FWS[3:0] - Flash Access Time Wait States (Defined in terms of AHB Clocks)
The FWS[3:0] field controls the number of extra clock cycles it takes to access the Flash memory and provide data back (to the bus or internal requester). The number of wait states needed is typically Taws/System Clock Period (or AHB Clock Period) rounded up to the nearest integer. If ECC is enabled an extra wait state may be needed. For additional information on the frequency range for each wait state selection, see Flash Controller Electrical Characteristics.
ADRWS - Address Wait State Enable
The ADRWS field controls the number of extra clock cycles for address setup to the Flash memory. The Address Wait state occurs before requesting arbitration, therefore it is in between the bus and the request to Flash. In most systems, the path starts at the initiator of the request.
When ADRWS = 0, no extra cycle clocks are added to address setup. When ADRWS = 1, one extra clock is added to address setup. ADRWS only affects AHB interfaces. It does not affect internal read requests, such as from CRC logic if present.
AUTOWS - Automatic Wait State Enable
The AUTOWS field controls the use of Automatic Wait state for the Flash access time (Taws). This is useful when varying clock frequencies.
When AUTOWS=1, the total Flash wait states are ADRWS+Taws. When AUTOWS = 0 the total Flash wait states are ADRWS+FWS. Non-CPU ports may incur an extra wait state. The bus might add pipeline delays to either the address phase or the data phase.
RDBUFWS[3:0] - Read Buffer Wait States
The RDBUFWS field controls the determinism of accesses from the read buffer. Each bit corresponds to an AHB Interface ‘n’. When RDBUFWS[n] = 0, the associated AHB interface returns data from the read buffer in zero wait states. When RDBUFWS[n] = 1, the associated AHB interface returns data with wait states to match the Flash access of ADRWS+FWS such that the initiator see a constant access time.
The setting of RDBUFWS[n] is ignored when AUTOWS = 1. For this case, all data is returned from the read buffer with zero wait states.
For devices with a Flash cache, RDBUFWS[n] applies to its interface only if the cache is disabled. Accesses to the flash from debug mode are completed through the read buffer.