4.2.1 JTAG
The JTAG interface consists of a 4-wire Test Access Port (TAP) controller that is compliant with the IEEE® 1149.1 standard. The IEEE standard was developed to provide an industry-standard way to efficiently test circuit board connectivity (Boundary Scan). Atmel AVR devices have extended this functionality to include full Programming and On-Chip Debugging support.
When designing an application PCB, which includes an Atmel AVR with the JTAG interface, it is recommended to use the pinout as shown in Figure 4-2. The JTAGICE3 can connect to both 100-mil and 50-mil variants of this pinout.
| Name | Pin | Description |
|---|---|---|
| TCK | 1 | Test Clock (clock signal from the JTAGICE3 into the target device) |
| TMS | 5 | Test Mode Select (control signal from the JTAGICE3 into the target device) |
| TDI | 9 | Test Data In (data transmitted from the JTAGICE3 into the target device) |
| TDO | 3 | Test Data Out (data transmitted from the target device into the JTAGICE3) |
| nTRST | 8 | Test Reset (optional, only on some AVR devices). Used to reset the JTAG TAP controller. |
| nSRST | 6 | Reset (optional) Used to reset the target device. Connecting this pin is recommended since it allows the JTAGICE3 to hold the target device in a reset state, which can be essential to debugging in certain scenarios. |
| VTG | 4 | Target voltage reference. The JTAGICE3 samples the target voltage on this pin in order to power the level converters correctly. The JTAGICE3 draws less than 1mA from this pin. |
| GND | 2, 10 | Ground. Both must be connected to ensure that the JTAGICE3 and the target device share the same ground reference. |
The JTAG interface allows for several devices to be connected to a single interface in a daisy-chain configuration. The target devices must all be powered by the same supply voltage, share a common ground node, and be connected as shown in the figure below.
When connecting devices in a daisy-chain, the following points must be considered:
- All devices must share a common ground connected to GND on the JTAGICE3 probe
- All devices must be operating on the same target voltage. VTG on the JTAGICE3 must be connected to this voltage.
- TMS and TCK are connected in parallel; TDI and TDO are connected in a serial chain.
- nSRST on the JTAGICE3 probe must be connected to RESET on the devices if any of the devices in the chain disables its JTAG port
- "Devices before" refers to the number of JTAG devices that the TDI signal has to pass through in the daisy chain before reaching the target device. Similarly "devices after" is the number of devices that the signal has to pass through after the target device before reaching the JTAGICE3 TDO pin.
- "Instruction bits before" and "after" refers to the sum of all JTAG devices' instruction register lengths, which are connected before and after the target device in the daisy chain
- The total IR length (instruction bits before + Atmel AVR IR length + instruction bits after) is limited to a maximum of 256 bits. The number of devices in the chain is limited to 15 before and 15 after.
Daisy chaining example: TDI → ATmega1280 → ATxmega128A1 → ATUC3A0512 → TDO
In order to connect to the Atmel AVR XMEGA device, the daisy chain settings are:
Devices before: 1
Devices after: 1
Instruction bits before: 4 (8-bit AVR devices have four IR bits)
Instruction bits before: 5 (32-bit AVR devices have five IR bits)