17.6.5 AHB Client Bus Interrupt Flag Status and Clear
| Name: | INTFLAGAHB |
| Offset: | 0x10 |
| Reset: | 0x00000000 |
| Property: | – |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BROM | SRAMDMAC | APBC | APBA | APBB | HSRAMDSU | HSRAMCM0P | FLASH | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – BROM CLIENT Boot ROM Interrupt Flag
A flag is cleared by writing a ‘1’ to it.
A flag is set when an access error is detected by client n and generates an
interrupt request if the Interrupt Enable Set (INTENSET.ERR) bit or Interrupt
Enable Clear (INTENCLR.ERR) bit is ‘1’.
Writing a ‘0’ to a bit has no effect.
Writing a ‘1’ to a bit will clear the corresponding interrupt
flag.
Bit 6 – SRAMDMAC CLIENT SRAMDMAC Interrupt Flag
A flag is cleared by writing a ‘1’ to it.
A flag is set when an access error is detected by client n and generates an
interrupt request if the Interrupt Enable Set (INTENSET.ERR) bit or Interrupt
Enable Clear (INTENCLR.ERR) bit is ‘1’.
Writing a ‘0’ to a bit has no effect.
Writing a ‘1’ to a bit will clear the corresponding interrupt
flag.
Bit 5 – APBC CLIENT APBC Interrupt Flag
A flag is cleared by writing a ‘1’ to it.
A flag is set when an access error is detected by client n and generates an
interrupt request if the Interrupt Enable Set (INTENSET.ERR) bit or Interrupt
Enable Clear (INTENCLR.ERR) bit is ‘1’.
Writing a ‘0’ to a bit has no effect.
Writing a ‘1’ to a bit will clear the corresponding interrupt
flag.
Bit 4 – APBA CLIENT APBA Interrupt Flag
A flag is cleared by writing a ‘1’ to it.
A flag is set when an access error is detected by client n and generates an
interrupt request if the Interrupt Enable Set (INTENSET.ERR) bit or Interrupt
Enable Clear (INTENCLR.ERR) bit is ‘1’.
Writing a ‘0’ to a bit has no effect.
Writing a ‘1’ to a bit will clear the corresponding interrupt
flag.
Bit 3 – APBB CLIENT APBB Interrupt Flag
A flag is cleared by writing a ‘1’ to it.
A flag is set when an access error is detected by client n and generates an
interrupt request if the Interrupt Enable Set (INTENSET.ERR) bit or Interrupt
Enable Clear (INTENCLR.ERR) bit is ‘1’.
Writing a ‘0’ to a bit has no effect.
Writing a ‘1’ to a bit will clear the corresponding interrupt
flag.
Bit 2 – HSRAMDSU CLIENT SRAMDSU Interrupt Flag
A flag is cleared by writing a ‘1’ to it.
A flag is set when an access error is detected by client n and generates an
interrupt request if the Interrupt Enable Set (INTENSET.ERR) bit or Interrupt
Enable Clear (INTENCLR.ERR) bit is ‘1’.
Writing a ‘0’ to a bit has no effect.
Writing a ‘1’ to a bit will clear the corresponding interrupt
flag.
Bit 1 – HSRAMCM0P CLIENT SRAMCM0P Interrupt Flag
A flag is cleared by writing a ‘1’ to it.
A flag is set when an access error is detected by client n and generates an
interrupt request if the Interrupt Enable Set (INTENSET.ERR) bit or Interrupt
Enable Clear (INTENCLR.ERR) bit is ‘1’.
Writing a ‘0’ to a bit has no effect.
Writing a ‘1’ to a bit will clear the corresponding interrupt
flag.
Bit 0 – FLASH CLIENT FLASH Interrupt Flag
A flag is cleared by writing a ‘1’ to it.
A flag is set when an access error is detected by client n and generates an
interrupt request if the Interrupt Enable Set (INTENSET.ERR) bit or Interrupt
Enable Clear (INTENCLR.ERR) bit is ‘1’.
Writing a ‘0’ to a bit has no effect.
Writing a ‘1’ to a bit will clear the corresponding interrupt
flag.