5.1.8 Strap Control 0 Register
Important: For proper device operation, do not change the
value of any bits in this register.
| Name: | STRAP_CTRL0 |
| Address: | 0x12 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| MITYP[1] | |||||||||
| Access | RO | RO | RO | RO | RO | RO | RO | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | x |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MITYP[0] | PKGTYP[1:0] | SMIADR[4:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | x | x | x | x | x | x | x | x | |
Bits 8:7 – MITYP[1:0] Media Interface Type - LAN8670 only
Note: This
bit field is undetermined in the LAN8671 and LAN8672.
| Value | Description |
|---|---|
00b |
Invalid external strap setting |
01b |
RMII MODE[1:0] = 10b |
10b |
MII MODE[1:0] = 01b |
11b |
Single Clock MII (SC-MII) MODE[1:0] = 11b |
Bits 6:5 – PKGTYP[1:0] Package Type
| Value | Description |
|---|---|
00b |
Invalid |
01b |
32-pin LAN8670 |
10b |
24-pin LAN8671 with RMII interface |
11b |
36-pin LAN8672 (Revision C2, only) with MII interface |
Bits 4:0 – SMIADR[4:0] Serial Management Interface Address
| Value | Description |
|---|---|
xxxxxb |
Serial Management Interface Address: LAN8670/2 |
0xxxxb |
Serial Management Interface Address: LAN8671 |
