5.1 SMI Basic Control and Status Registers
The section describes the various SMI Control and Status Registers (CSRs). The SMI CSRs follow the IEEE 802.3 (Clause 22.2.4) management register set. All functionality and bit definitions comply with these standards.
Important: RESERVED address space must not be written to
except when specifically directed to by Microchip. Failure to heed this warning may result
in adverse operation and unexpected results.
| Address | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 | BASIC_CONTROL | 15:8 | SW_RESET | LOOPBACK | SPD_SEL[0] | AUTONEGEN | PD | ISOLATE | REAUTONEG | DUPLEXMD |
| 7:0 | COLTST | SPD_SEL[1] | ||||||||
| 0x01 | BASIC_STATUS | 15:8 | 100BT4A | 100BTXFDA | 100BTXHDA | 10BTFDA | 10BTHDA | 100BT2FDA | 100BT2HDA | EXTSTS |
| 7:0 | MFPRESUPA | AUTONEGC | RMTFLTD | AUTONEGA | LNKSTS | JABDET | EXTCAPA | |||
| 0x01 | BASIC_STATUS - Rev D | 15:8 | 100BT4A | 100BTXFDA | 100BTXHDA | 10BTFDA | 10BTHDA | 100BT2FDA | 100BT2HDA | EXTSTS |
| 7:0 | MFPRESUPA | AUTONEGC | RMTFLTD | AUTONEGA | LNKSTS | JABDET | EXTCAPA | |||
| 0x02 | PHY_ID1 | 15:8 | OUI[2:9] | |||||||
| 7:0 | OUI[10:17] | |||||||||
| 0x03 | PHY_ID2 | 15:8 | OUI[18:23] | MODEL[5:4] | ||||||
| 7:0 | MODEL[3:0] | REV[3:0] | ||||||||
0x05 ... 0x0C | Reserved | |||||||||
| 0x0D | MMDCTRL | 15:8 | FNCTN[1:0] | |||||||
| 7:0 | DEVAD[4:0] | |||||||||
| 0x0E | MMDAD | 15:8 | ADR_DATA[15:8] | |||||||
| 7:0 | ADR_DATA[7:0] | |||||||||
0x10 ... 0x11 | Reserved | |||||||||
| 0x12 | STRAP_CTRL0 | 15:8 | MITYP[1] | |||||||
| 7:0 | MITYP[0] | PKGTYP[1:0] | SMIADR[4:0] | |||||||