5.2.4 10BASE-T1S PMA Control - Rev D

This register is only valid for devices of Revision D0 and later.

Name:	T1SPMACTL - Rev D
Address:	0x08F9


Bit	15	14	13	12	11	10	9	8
	RST	TXD			LPE	MDE
Access	R/W SC	R/W	RO	RO	R/W	RO	RO	RO
Reset	0	0	0	0	0	1	0	0


Bit	7	6	5	4	3	2	1	0
								LBE
Access	RO	RO	RO	RO	RO	RO	RO	R/W
Reset	0	0	0	0	0	0	0	0

Bit 15 – RST PMA Reset

Setting this bit will reset the device PMA.

Note: This bit is self-clearing. When setting this bit, do not set other bits in this register.

Value	Description
`0`	Normal Operation
`1`	PMA Reset

Bit 14 – TXD Transmit Disable

The PMA transmit path is disabled when this bit is set. This bit must be clear for normal operation.

Value	Description
`0`	Normal operation
`1`	Transmit disable

Bit 11 – LPE Low Power Enable

Setting this bit will power down the PMA.

Note: This bit has the same effect as the Power Down bit in the Clause 22 BASIC_CONTROL register.

Value	Description
`0`	Normal operation
`1`	Place PMA into low-power mode

Bit 10 – MDE Multidrop Mode

When set, this bit will enable multidrop operation on a mixing segment.

Note: This bit has no effect on the operation of the device.

Value	Description
`0`	Mixing segment operation disabled (point-to-point mode)
`1`	PMA multidrop (mixing segment) operation enabled

Bit 0 – LBE PMA Loopback Enable

This bit will enable the PMA loopback test mode when set. Data received from the MAC via the media interface will be passed through the PCS scrambler/descrambler, 4B/5B encoder/decoder, and the PMA differential Manchester encoder/decoder and returned back to the MAC.

Important: PLCA must be disabled or configured as the PLCA Coordinator (Local ID = 0) when the PMA loopback mode is enabled.

Value	Description
`0`	Disable PMA loopback mode
`1`	Enable PMA loopback mode

LAN8670/1