5.2 μSRAM Macro

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The μSRAM macro (RAM64x12) in Libero SoC can be used directly to instantiate μSRAM in the design. μSRAM must be configured correctly with appropriate values provided to the static signals before instantiating in the design. Instantiating μSRAM primitives in a design is not recommended. For the recommended methods of instantiating memory into a user design, see μSRAM Memory Macro. The following figure shows the μSRAM macro (RAM64x12) available in the Libero SoC macro library.

The following table lists the ports of RAM64x12.

Table 5-10. Port List for RAM64x12
Pin Name	Direction	Type¹	Polarity	Description
W_EN	Input	Dynamic	Active high	Write port enable
W_CLK	Input	Dynamic	Rising edge	Write clock. All write-address, write-data, and write-enable inputs must be set up before the rising edge of the clock. The write operation begins with the rising edge.
W_ADDR[5:0]	Input	Dynamic	—	Write address
W_DATA[11:0]	Input	Dynamic		Write-data
BLK_EN	Input	Dynamic	Active high	Read port block select. When High, a read operation is performed. When Low, read-data is forced to zero. BLK_EN signal is registered through R_CLK when R_ADDR_BYPASS is Low.
R_CLK	Input	Dynamic	Rising edge	Read registers clock. All read-address, block-port select, and read-enable inputs must be set up before the rising edge of the clock. The read operation begins with the rising edge.
R_ADDR[]	Input	Dynamic		Read-address
R_ADDR_BYPASS	Input	Static	Active high	Read-address and BLK_EN register bypassed when high
R_ADDR_EN	Input	Dynamic	Active high	Read-address register enable
R_ADDR_SL_N	Input	Dynamic	Active low	Read-address register synchronous load
R_ADDR_SD	Input	Static	Active high	Read-address register synchronous load data
R_ADDR_AL_N	Input	Dynamic	Active low	Read-address register asynchronous load
R_ADDR_AD_N	Input	Static	Active low	Read-address register asynchronous load data
R_DATA[]	Output	Dynamic		Read-data
R_DATA_BYPASS	Input	Static	Active high	Read-data pipeline register bypassed when high
R_DATA_EN	Input	Dynamic	Active high	Read-data pipeline register enable
R_DATA_SL_N	Input	Dynamic	Active low	Read-data pipeline register synchronous load
R_DATA_SD	Input	Static	Active high	Read-data pipeline register synchronous load data
R_DATA_AL_N	Input	Dynamic	Active low	Read-data pipeline register asynchronous load
R_DATA_AD_N	Input	Static	Active low	Read-data pipeline register asynchronous load data
BUSY_FB	Input	Static	Active high	Lock access to SmartDebug
ACCESS_BUSY	Output	Dynamic	Active high	Busy signal from SmartDebug
Note: ⁽¹⁾ Static inputs are defined at design time and need to be tied to 0 or 1.