5.1 LSRAM Macro

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The LSRAM macro (RAM1K20) in the Libero SoC IP macro library can be used directly to instantiate the LSRAM block in the design. The LSRAM block must be configured with appropriate values of the static signals. Instantiating LSRAM primitives in a design is not recommended. For the recommended methods of instantiating memory in a user design, see LSRAM Memory Macro. The following figure shows the LSRAM macro (RAM1K20).

The following table lists the ports of RAM1K20.

Table 5-1. Port List of RAM1K20
Pin Name	Direction	Type¹	Polarity	Description
A_ADDR[13:0]	Input	Dynamic	—	Port A address
BLK_EN[2:0]	Input	Dynamic	Active High	Port A block selects
A_CLK	Input	Dynamic	Rising edge	Port A clock
A_DIN[19:0]	Input	Dynamic	—	Port A write data
A_DOUT[19:0]	Output	Dynamic	—	Port A read data
A_WEN[1:0]	Input	Dynamic	Active High	Port A write-enables (per byte)
A_REN	Input	Dynamic	Active High	Port A read-enable
A_WIDTH[2:0]	Input	Static	—	Port A width/depth mode select
A_WMODE[1:0]	Input	Static	Active High	Port A read-before-write and feed-through write selects
A_BYPASS	Input	Static	Active High	Port A pipeline register bypassed when High
A_DOUT_EN	Input	Dynamic	Active High	Port A pipeline register enable
A_DOUT_SRST_N	Input	Dynamic	Active Low	Port A pipeline register synchronous reset
A_DOUT_ARST_N	Input	Dynamic	Active Low	Port A pipeline register asynchronous reset
B_ADDR[13:0]	Input	Dynamic	—	Port B address
B_BLK_EN[2:0]	Input	Dynamic	Active High	Port B block selects
B_CLK	Input	Dynamic	Rising edge	Port B clock
B_DIN[19:0]	Input	Dynamic	—	Port B write data
B_DOUT[19:0]	Output	Dynamic	—	Port B read data
B_WEN[1:0]	Input	Dynamic	Active High	Port B write-enables (per byte)
B_REN	Input	Dynamic	Active High	Port B read-enable
B_WIDTH[2:0]	Input	Static	Mode select	Port B width/depth mode select
B_WMODE[1:0]	Input	Static	Active High	Port B read-before-write and feed-through write selects
B_BYPASS	Input	Static	Active High	Port B pipeline register bypassed when High
B_DOUT_EN	Input	Dynamic	Active High	Port B pipeline register enable
B_DOUT_SRST_N	Input	Dynamic	Active Low	Port B pipeline register synchronous-reset
B_DOUT_ARST_N	Input	Dynamic	Active Low	Port B pipeline register asynchronous-reset
ECC_EN	Input	Static	Active High	Enable ECC
ECC_BYPASS	Input	Static	Active High	ECC pipeline register bypassed when High
SB_CORRECT	Output	Dynamic	Active High	Single-bit correct flag
DB_DETECT	Output	Dynamic	Active High	Double-bit detect flag
BUSY_FB	Input	Static	Active High	Lock access to SmartDebug
ACCESS_BUSY	Output	Dynamic	Active High	Busy signal when being initialized or accessed using SmartDebug

Note:

Static inputs are defined at design time and need to be tied to 0 or 1.