5.3.1.1 Port List

The following table lists the MACC_PA ports.

Table 5-12. MACC_PA Pin Descriptions
Port Name	Direction	Type ¹	Polarity	Description
DOTP	Input	Static	Active high	DOTP mode When DOTP = 1, MACC_PA block performs DOTP of two pairs of 9-bit operands. • SIMD must not be 1 • C[8:0] must be connected to CARRYIN.
SIMD	Input	Static	Active high	SIMD mode When SIMD = 1, MACC_PA block performs dual-independent multiplication of two pairs of 9-bit operands. DOTP must not be 1 ARSHFT17 must be 0 D[8:0] must be 0 C[17:0] must be 0 E[17:0] must be 0. For more information about how operand E is obtained from P, CDIN, or 0, see Table 3-3.
OVFL_CARRYOUT_SEL	Input	Static	Active high	Generate OVERFLOW or CARRYOUT with result P. OVERFLOW when OVFL_CARRYOUT_SEL = 0 CARRYOUT when OVFL_CARRYOUT_SEL = 1
CLK	Input	Dynamic	Rising edge	Clock for A, B, C, CARRYIN, D, P, OVFL_CARRYOUT, ARSHFT17, CDIN_FDBK_SEL, PASUB, and SUB registers.
AL_N	Input	Dynamic	Active low	Asynchronous load for A, B, P, OVFL_CARRYOUT, ARSHFT17, CDIN_FDBK_SEL, PASUB, and SUB registers. Connect to 1 if not registered. When asserted, A, B, P, and OVFL_CARRYOUT registers are loaded with zero, while the ARSHFT17, CDIN_FDBK_SEL, PASUB, and SUB registers are loaded with the complementary value of the respective _AD_N.
A[17:0]	Input	Dynamic	Active high	Input data A
A_BYPASS	Input	Static	Active high	Bypass data A registers. Connect to 1 if not registered. For more information, see Table 5-14.
A_SRST_N	Input	Dynamic	Active low	Synchronous reset for data A registers. Connect to 1 if not registered. For more information, see Table 5-14.
A_EN	Input	Dynamic	Active high	Enable for data A registers. Connect to 1 if not registered. For more information, see Table 5-14.
B[17:0]	Input	Dynamic	Active high	Input data B to pre-adder with data D.
B_BYPASS	Input	Static	Active high	Bypass data B registers. Connect to 1 if not registered. For more information, see Table 5-14.
B_SRST_N	Input	Dynamic	Active low	Synchronous reset for data B registers. Connect to 1 if not registered. For more information, see Table 5-14.
B_EN	Input	Dynamic	Active high	Enable for data B registers. Connect to 1 if not registered. For more information, see Table 5-14.
D[17:0]	Input	Dynamic	Active high	Input data D to pre-adder with data B. When SIMD = 1, connect D[8:0] to 0.
D_BYPASS	Input	Static	Active high	Bypass data D registers. Connect to 1 if not registered. For more information, see Table 5-15.
D_ARST_N	Input	Dynamic	Active low	Asynchronous reset for data D registers. Connect to 1 if not registered. For more information, see Table 5-15.
D_SRST_N	Input	Dynamic	Active low	Synchronous reset for data D registers. Connect to 1 if not registered. For more information, see Table 5-15.
D_EN	Input	Dynamic	Active high	Enable for data D registers. Connect to 1 if not registered. For more information, see Table 5-15.
CARRYIN	Input	Dynamic	Active high	CARRYIN for input data C.
C[47:0]	Input	Dynamic	Active high	Input data C. When DOTP = 1, connect C[8:0] to CARRYIN. When SIMD = 1, connect C[8:0] to 0.
C_BYPASS	Input	Static	Active high	Bypass CARRYIN and C registers. Connect to 1 if not registered. For more information, see Table 5-15.
C_ARST_N	Input	Dynamic	Active low	Asynchronous reset for CARRYIN and C registers. Connect to 1 if not registered. For more information, see Table 5-15.
C_SRST_N	Input	Dynamic	Active low	Synchronous reset for CARRYIN and C registers. Connect to 1 if not registered. For more information, see Table 5-15.
C_EN	Input	Dynamic	Active high	Enable for CARRYIN and C registers. Connect to 1 if not registered. For more information, see Table 5-15.
CDIN[47:0]	Input	Cascade	Active high	Cascaded input for operand E. The entire bus must be driven by an entire CDOUT of another MACC_PA or MACC_PA_BC_ROM block. In DOTP mode, the driving CDOUT must also be generated by a MACC_PA or MACC_PA_BC_ROM block in DOTP mode. For more information about how CDIN is propagated to operand E, see Table 3-3.
P[47:0]	Output		Active high	Result data. For more information, see Table 3-4.
OVFL_CARRYOUT	Output		Active high	OVERFLOW or CARRYOUT. For more information, see Table 3-4.
P_BYPASS	Input	Static	Active high	Bypass P and OVFL_CARRYOUT registers. Connect to 1 if not registered. For more information, see Table 5-14.
P_SRST_N	Input	Dynamic	Active low	Synchronous reset for P and OVFL_CARRYOUT registers. Connect to 1 if not registered. For more information, see Table 5-14.
P_EN	Input	Dynamic	Active high	Enable for P and OVFL_CARRYOUT registers. Connect to 1 if not registered. For more information, see Table 5-14.
CDOUT[47:0]	Output	Cascade	Active high	Cascade output of result P. For more information, see Table 3-4. Value of CDOUT is the same as P. The entire bus must either be dangling or drive an entire CDIN of another MACC_PA or MACC_PA_BC_ROM block in cascaded mode.
PASUB	Input	Dynamic	Active high	Subtract operation for pre-adder of B and D.
PASUB_BYPASS	Input	Static	Active high	Bypass PASUB register. Connect to 1 if not registered. For more information, see Table 5-13.
PASUB_AD_N	Input	Static	Active low	Asynchronous load data for PASUB register. For more information, see Table 5-13.
PASUB_SL_N	Input	Dynamic	Active low	Synchronous load for PASUB register. Connect to 1 if not registered. For more information, see Table 5-13.
PASUB_SD_N	Input	Static	Active low	Synchronous load data for PASUB register. For more information, see Table 5-13.
PASUB_EN	Input	Dynamic	Active high	Enable for PASUB register. Connect to 1 if not registered. For more information, see Table 5-13.
CDIN_FDBK_SEL[1:0]	Input	Dynamic	Active high	Select CDIN, P or 0 for operand E. For more information, see Table 3-3.
CDIN_FDBK_SEL_BYPASS	Input	Static	Active high	Bypass CDIN_FDBK_SEL register. Connect to 1 if not registered. For more information, see Table 5-13.
CDIN_FDBK_SEL_AD_N [1:0]	Input	Static	Active low	Asynchronous load data for CDIN_FDBK_SEL register. For more information, see Table 5-13.
CDIN_FDBK_SEL_SL_N	Input	Dynamic	Active low	Synchronous load for CDIN_FDBK_SEL register. Connect to 1 if not registered. For more information, see Table 5-13.
CDIN_FDBK_SEL_SD_N [1:0]	Input	Static	Active low	Synchronous load data for CDIN_FDBK_SEL register. For more information, see Table 5-13.
CDIN_FDBK_SEL_EN	Input	Dynamic	Active high	Enable for CDIN_FDBK_SEL register. Connect to 1 if not registered. For more information, see Table 5-13.
ARSHFT17	Input	Dynamic	Active high	Arithmetic right-shift for operand E. When asserted, a 17-bit arithmetic right-shift is performed on operand E. For information on how operand E is obtained from P, CDIN or 0, see Table 3-3. When SIMD = 1, ARSHFT17 must be 0.
ARSHFT17_BYPASS	Input	Static	Active high	Bypass ARSHFT17 register. Connect to 1 if not registered. For more information, see Table 5-13.
ARSHFT17_AD_N	Input	Static	Active low	Asynchronous load data for ARSHFT17 register. For more information, see Table 5-13.
ARSHFT17_SL_N	Input	Dynamic	Active low	Synchronous load for ARSHFT17 register. Connect to 1 if not registered. For more information, see Table 5-13.
ARSHFT17_SD_N	Input	Static	Active low	Synchronous load data for ARSHFT17 register. For more information, see Table 5-13.
ARSHFT17_EN	Input	Dynamic	Active high	Enable for ARSHFT17 register. Connect to 1 if not registered. For more information, see Table 5-13.
SUB	Input	Dynamic	Active high	Subtract operation.
SUB_BYPASS	Input	Static	Active high	Bypass SUB register. Connect to 1 if not registered. For more information, see Table 5-13.
SUB_AD_N	Input	Static	Active low	Asynchronous load data for SUB register. For more information, see Table 5-13.
SUB_SL_N	Input	Dynamic	Active low	Synchronous load for SUB register. Connect to 1 if not registered. For more information, see Table 5-13.
SUB_SD_N	Input	Static	Active low	Synchronous load data for SUB register. For more information, see Table 5-13.
SUB_EN	Input	Dynamic	Active high	Enable for SUB register. Connect to 1 if not registered. For more information, see Table 5-13.
Note: ⁽¹⁾ Static inputs are defined at design time and need to be tied to 0 or 1.

Note: SUM[49:0] is defined similarly to P[47:0] as listed in Table 3-4, except that SUM is a 50-bit quantity so that overflow does not occur. SUM[48] is the carry out bit of a 48-bit final adder that produces P[47:0].

Table 5-13. Truth Table for Control Registers ARSHFT17, CDIN_FDBK_SEL, PASUB, and SUB
AL_N	_AD_N	_BYPASS	CLK	_EN	_SL_N	_SD_N	D	Qn+1
0	AD_N	0	X	X	X	X	X	!AD_N
1	X	0	Not rising	X	X	X	X	Qn
1	X	0	↑	0	X	X	X	Qn
1	X	0	↑	1	0	SD_N	X	!SD_N
1	X	0	↑	1	1	X	D	D
X	X	1	X	0	X	X	X	Qn
X	X	1	X	1	0	SD_N	X	!SD_N
X	X	1	X	1	1	X	D	D

Table 5-14. Truth Table for Data Registers A, B, P, and OVFL_CARRYOUT
AL_N	_BYPASS	CLK	_EN	_SRST_N	D	Qn+1
0	0	X	X	X	X	0
1	0	Not rising	X	X	X	Qn
1	0	↑	0	X	X	Qn
1	0	↑	1	0	X	0
1	0	↑	1	1	D	D
X	1	X	0	X	X	Qn
X	1	X	1	0	X	0
X	1	X	1	1	D	D

Table 5-15. Truth Table for Data Registers C, CARRYIN, and D
_ARST_N	_BYPASS	CLK	_EN	_SRST_N	D	Qn+1
0	0	X	X	X	X	0
1	0	Not rising	X	X	X	Qn
1	0	↑	0	X	X	Qn
1	0	↑	1	0	X	0
1	0	↑	1	1	D	D
X	1	X	0	X	X	Qn
X	1	X	1	0	X	0
X	1	X	1	1	D	D