2.2 μSRAM

Each μSRAM has one read port and one write port for Two-Port memory requirements. The following figure shows the μSRAM I/O diagram.

Figure 2-25. µSRAM Input/Output

The following table lists the ports available in μSRAM.

Table 2-16. Port List for μSRAM
Pin NameDirectionType1PolarityDescription
W_ENInputDynamicActive HighWrite enable
W_CLKInputDynamicRising edgeWrite clock
W_ADDR[5:0]InputDynamic—Write address
W_DATA[11:0]InputDynamic—Write-data
BLK_ENInputDynamicActive HighRead port enable
R_CLKInputDynamicRising edgeRead clock
R_ADDR[5:0]InputDynamic—Read-address
R_ADDR_BYPASSInputStaticActive HighRead-address and BLK_EN bypassed when High
R_ADDR_ENInputDynamicActive HighRead-address register Enable
R_ADDR_SL_NInputDynamicActive LowRead-address register synchronous load
R_ADDR_SDInputStaticActive HighRead-address register synchronous load data
R_ADDR_AL_NInputDynamicActive LowRead-address register asynchronous load
R_ADDR_AD_NInputStaticActive LowRead-address register asynchronous load data
R_DATA[11:0]OutputDynamic—Read-data
R_DATA_BYPASSInputStaticActive HighRead-data pipeline register bypassed when High
R_DATA_ENInputDynamicActive HighRead-data pipeline register enable
R_DATA_SL_NInputDynamicActive LowRead-data pipeline register synchronous load
R_DATA_SDInputStaticActive HighRead-data pipeline register synchronous load data
R_DATA_AL_NInputDynamicActive LowRead-data pipeline register asynchronous load
R_DATA_AD_NInputStaticActive LowRead-data pipeline register asynchronous load data
BUSY_FBInputStaticActive HighLock access to SmartDebug
ACCESS_BUSYOutputDynamicActive HighBusy signal when the RAM is being initialized or accessed using SmartDebug
Note:
  1. Static inputs are tied to 0 or 1 during design implementation.

The following figure shows the μSRAM with independent write and read ports and read data pipeline registers.

Figure 2-26. Simplified Functional Block Diagram of µSRAM