2.1 LSRAM

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Each LSRAM has two independent ports—Port A and Port B, as shown in Figure 1. Both these ports support write and read operations, and can be configured in dual-port mode or two-port mode.

Important: When ECC is enabled, if a single-bit error occurs in a word, the data is corrected. If multiple-bit errors occur in a word, the data from the LSRAM is not corrected or modified.

The following table lists the ports of LSRAM.

Table 2-2. LSRAM Port List
Port Name	Direction	Type¹	Polarity	Description
Port A
A_ADDR[13:0]	Input	Dynamic	—	Port A address
A_BLK_EN[2:0]	Input	Dynamic	Active high	Port A block selects
A_CLK	Input	Dynamic	Rising edge	Port A clock
A_DIN[19:0]	Input	Dynamic	—	Port A write-data
A_DOUT[19:0]	Output	Dynamic	—	Port A read-data
A_WEN[1:0]	Input	Dynamic	Active high	Port A byte write-enables
A_REN	Input	Dynamic	Active high	Port A read-enable
A_WIDTH[2:0]	Input	Static	—	Port A width/depth mode select
A_WMODE[1:0]	Input	Static	Active high	Port A read-before-write and feed-through write selects
A_BYPASS	Input	Static	Active high	Port A read data pipeline register bypassed when High
A_DOUT_EN	Input	Dynamic	Active high	Port A pipeline register enable
A_DOUT_SRST_N	Input	Dynamic	Active low	Port A pipeline register synchronous-reset
A_DOUT_ARST_N	Input	Dynamic	Active low	Port A pipeline register asynchronous-reset
Port B
B_ADDR[13:0]	Input	Dynamic	—	Port B address
B_BLK_EN[2:0]	Input	Dynamic	Active high	Port B block selects
B_CLK	Input	Dynamic	Rising edge	Port B clock
B_DIN[19:0]	Input	Dynamic	—	Port B write-data
B_DOUT[19:0]	Output	Dynamic	—	Port B read-data
B_WEN[1:0]	Input	Dynamic	Active high	Port B write-enables (per byte)
B_REN	Input	Dynamic	Active high	Port B read-enable
B_WIDTH[2:0]	Input	Static	Mode select	Port B width/depth
B_WMODE[1:0]	Input	Static	Active high	Port B read-before-write and feed-through write selects
B_BYPASS	Input	Static	Active high	Port B read data pipeline register bypassed when High
B_DOUT_EN	Input	Dynamic	Active high	Port B pipeline register enable
B_DOUT_SRST_N	Input	Dynamic	Active low	Port B pipeline register synchronous-reset
B_DOUT_ARST_N	Input	Dynamic	Active low	Port B pipeline register asynchronous-reset
Common Signals
ECC_EN	Input	Static	Active high	Enable ECC
ECC_BYPASS	Input	Static	Active high	ECC pipeline register bypassed when High.
SB_CORRECT	Output	Dynamic	Active high	Single-bit correct flag
DB_DETECT	Output	Dynamic	Active high	Dual-bit error detect flag
BUSY_FB	Input	Static	Active high	Lock access to SmartDebug
ACCESS_BUSY	Output	Dynamic	Active high	Busy signal from SmartDebug

Note:

Static inputs are tied to 0 or 1 during design implementation.