2.1.2 Two-Port Mode

The LSRAM block can be configured as a Two-Port SRAM, where Port A is dedicated to read operations and Port B is dedicated to write operations for data widths up to x20. For data widths greater than x20, the read port borrows the unused Port B data output signals, similarly write port borrows the unused Port A data input signals. Figure   1 shows the LSRAM in Two-Port mode with independent write and read ports, pipeline registers, ECC logic, and feed-through MUXes to enable immediate access to the write data. The ECC is supported only when the LSRAM is configured for 33-bit data width.