33.6.3.5 Hardware Controlled SS

In Host mode, a single SS chip select can be controlled by hardware by writing the Host SPI Select Enable (CTRLB.MSSEN) bit to ‘1’. In this mode, the SS pin is driven low for a minimum of one baud cycle before transmission begins, and stays low for a minimum of one baud cycle after transmission completes. If back-to-back frames are transmitted, the SS pin will always be driven high for a minimum of one baud cycle between frames.

In the following figure, the time, T, is between one and two baud cycles depending on the SPI Transfer mode.

When CTRLB.MSSEN = 0, the SS pin(s) is/are controlled by user software and normal GPIO.