33.6.3.8 32-Bit Extension

For better system bus utilization, 32-bit data receive and transmit can be enabled by writing to the Data 32-bit bit field in the Control C register (CTRLC.DATA32B = 1). When enabled, write and read transactions to/from the DATA register are 32 bits in size.

If frames are not multiples of 4 bytes, the Length Counter (LENGTH.LEN) and Length Enable (LENGTH.LENEN) must be configured before data transfer begins. LENGTH.LEN must be enabled only when CTRLC.DATA32B is enabled.

The following figure illustrates the order of transmit and receive when using 32-bit mode. Bytes are transmitted or received and stored in order from 0 to 3.

Only 8-bit character size is supported.

Figure 33-9. 32-Bit Extension Byte Ordering

32-Bit Extension Client Operation

The following figure illustrates a transaction with 32-bit Extension enabled (CTRLC.DATA32B = 1). When address recognition is enabled (CTRLA.FORM = 0x2) and there is an address match, the address is loaded into the FIFO as Byte zero and data begins with Byte 1. INTFLAGS.RXC will, then, be raised for every 4 bytes transferred. For transmit, there is a 32-bit holding buffer in the core domain. After DATA is registered in the core domain, INTFLAG.DRE is raised so that the next 32 bits can be written to the DATA register.

Figure 33-10. 32-Bit Extension Client Operation

When utilizing the length counter, the LENGTH register must be written before the frame begins. If the frame length while SS is low is not a multiple of LENGTH.LEN bytes, the Length Error Status bit (STATUS.LENERR) is raised. If LENGTH.LEN is not a multiple of 4 bytes, the final INTFLAG.RXC interrupt is raised when the last byte is received.

The length count is based on the received bytes or the number of clocks if the receiver is not enabled. If pre-loading is disabled and DATA is written for transmit before SCK starts, transmitted data are delayed by one byte, but the length counter will still increment for the first (empty) byte transmission. When the counter reaches LENGTH.LEN, the internal length counter, RX byte counter and TX byte counter are reset. If multiple lengths are to be transmitted, INTFLAG.TXC must go high before writing DATA for subsequent lengths.

If there is a Length Error (STATUS.LENERR), the remaining bytes in the length are transmitted at the beginning of the next frame. If this is not desired, the SERCOM must be disabled and re-enabled to flush the TX and RX pipelines.

Writing the LENGTH register while a frame is in progress produces unpredictable results. If LENGTH.LENEN is not configured and a frame is not a multiple of 4 bytes (while SS is low), the remainder is transmitted in the next frame.

32-Bit Extension Host Operation

When using the SPI configured as the host, the Length and the Length Enable bit fields (LENGTH.LEN and LENGTH.LENEN) must be written before the frame begins. When LENGTH.LENEN is written to ‘1’, the value of LENGTH.LEN determines the number of data bytes in the transaction from 1 to 255.

For receive data, INTFLAG.RXC is raised every 4 bytes received. If LENGTH.LEN is not a multiple of 4 bytes, the final INTFLAG.RXC is set when the final byte is received.

For transmit, there is a holding buffer for the 32-bit data in the core domain. After DATA is registered in the SCK domain, INTFLAG.DRE is raised so that the next 32 bits can be written to the DATA register.

If multiple lengths are to be transmitted, INTFLAG.TXC must go high before writing DATA for subsequent lengths.