38.7.12 Comparator Control n

Name: COMPCTRL
Offset: 0x10 + n*0x04 [n=0..1]
Reset: 0x00000000
Property: PAC Write-Protection

Bit 3130292827262524 
   OUT[1:0] FLEN[2:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
 SWAPMUXPOS[2:0] MUXNEG[2:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 
Bit 76543210 
  RUNSTDBY INTSEL[1:0]SINGLEENABLE  
Access R/WR/WR/WR/WR/W 
Reset 00000 

Bits 29:28 – OUT[1:0] Output

These bits configure the output selection for Comparator n. COMPCTRLn.OUT can be written only while COMPCTRLn.ENABLE is ‘0’.

Note: For internal use of the comparison results by the CCL, this must be 0x1 or 0x2.

These bits are not synchronized.

ValueNameDescription
0x0OFFThe output of COMPn is not routed to the COMPn I/O port
0x1ASYNCThe asynchronous output of COMPn is routed to the COMPn I/O port
0x2SYNCThe synchronous output (including filtering) of COMPn is routed to the COMPn I/O port
0x3N/AReserved

Bits 26:24 – FLEN[2:0] Filter Length

These bits configure the filtering for Comparator n. COMPCTRLn.FLEN can only be written while COMPCTRLn.ENABLE is ‘0’.

These bits are not synchronized.

ValueNameDescription
0x0OFFNo filtering
0x1MAJ33-bit majority function (2 of 3)
0x2MAJ55-bit majority function (3 of 5)
0x3-0x7N/AReserved

Bit 15 – SWAP Swap Inputs and Invert

This bit swaps the positive and negative inputs to COMPn and inverts the output. This function can be used for offset cancellation. COMPCTRLn.SWAP can be written only while COMPCTRLn.ENABLE is ‘0’.

These bits are not synchronized.

ValueDescription
0The output of MUXPOS connects to the positive input, and the output of MUXNEG connects to the negative input.
1The output of MUXNEG connects to the positive input, and the output of MUXPOS connects to the negative input.

Bits 14:12 – MUXPOS[2:0] Positive Input Mux Selection

These bits select which input is connected to the positive input of Comparator n. COMPCTRLn.MUXPOS can be written only while COMPCTRLn.ENABLE is ‘0’.

These bits are not synchronized.

ValueNameDescription
0x0PIN0AC_AIN0
0x1PIN1AC_AIN1
0x2PIN2AC_AIN2
0x3PIN3AC_AIN3
0x4VSCALEVDD scaler
0x5–0x7Reserved

Bits 10:8 – MUXNEG[2:0] Negative Input Mux Selection

These bits select which input is connected to the negative input of Comparator n. COMPCTRLn.MUXNEG can only be written while COMPCTRLn.ENABLE is ‘0’.

These bits are not synchronized.

ValueNameDescription
0x0PIN0I/O pin 0
0x1PIN1I/O pin 1
0x2PIN2I/O pin 2
0x3PIN3I/O pin 3
0x4GNDGround
0x5VSCALEVDD scaler
0x6BANDGAPInternal bandgap voltage
0x7DACDAC output

Bit 6 – RUNSTDBY Run in Standby

This bit controls the behavior of the comparator during Standby Sleep mode.

This bit is not synchronized

ValueDescription
0The comparator is disabled during sleep.
1The comparator continues to operate during sleep.

Bits 4:3 – INTSEL[1:0] Interrupt Selection

These bits select the condition for Comparator n to generate an interrupt or event. COMPCTRLn.INTSEL can be written only while COMPCTRLn.ENABLE is ‘0’.

These bits are not synchronized.

ValueNameDescription
0x0TOGGLEInterrupt on comparator output toggle
0x1RISINGInterrupt on comparator output rising
0x2FALLINGInterrupt on comparator output falling
0x3EOCInterrupt on end of comparison (Single-shot mode only)

Bit 2 – SINGLE Single-Shot Mode

This bit determines the operation of Comparator n. COMPCTRLn.SINGLE can be written only while COMPCTRLn.ENABLE is ‘0’.

These bits are not synchronized.

ValueDescription
0Comparator n operates in continuous Measurement mode.
1Comparator n operates in Single-shot mode.

Bit 1 – ENABLE Enable

Writing a ‘0’ to this bit disables Comparator n.
Writing a ‘1’ to this bit enables Comparator n.

Due to synchronization, there is a delay from updating the register until the comparator is enabled/disabled. The value written to COMPCTRLn.ENABLE reads back immediately after being written. SYNCBUSY.COMPCTRLn is set. SYNCBUSY.COMPCTRLn is cleared when the peripheral is enabled/disabled.

Writing a ‘1’ to COMPCTRLn.ENABLE prevents further changes to the other bits in COMPCTRLn. These bits remain protected until COMPCTRLn.ENABLE is written to ‘0’ and the write is synchronized.