27.8.1 Control A

The EIC can be clocked either by GCLK_EIC (when a frequency higher than 32.768 KHz is required for filtering) or by 32KHz_LPCLK (when power consumption is the priority).

This bit is not Write-Synchronized.

Due to synchronization, there is a delay between writing to CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy register is set (SYNCBUSY.ENABLE=1). SYNCBUSY.ENABLE is cleared when the operation is complete.

This bit is not Enable-Protected.

This bit is Write-Synchronized.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit resets all registers in the EIC to their initial state, and the EIC is disabled.

Writing a ‘1’ to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write operation are discarded.

Due to synchronization, there is a delay from writing CTRLA.SWRST until the Reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the Reset is complete.

This bit is not Enable-Protected.

This bit is Write-Synchronized.