27.8.7 Interrupt Enable Set
Name: | INTENSET |
Offset: | 0x10 |
Reset: | 0x00000000 |
Property: | PAC Write-Protection |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
EXTINT[3:0] | |||||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 0 | 0 | 0 |
Bits 3:0 – EXTINT[3:0] External Interrupt Enable
The bit x of EXTINT enables the interrupt associated with the EXTINTx pin.
Writing a ‘0
’ to bit x has no effect.
Writing a ‘1
’ to bit x will set the External
Interrupt Enable bit x, which enables the external interrupt EXTINTx.
Value | Description |
---|---|
0 | The external interrupt x is disabled. |
1 | The external interrupt x is enabled. |