27.8.2 Non-Maskable Interrupt Control
| Name: | NMICTRL |
| Offset: | 0x01 |
| Reset: | 0x00 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| NMIASYNCH | NMIFILTEN | NMISENSE[2:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bit 4 – NMIASYNCH Non-Maskable Interrupt Asynchronous Edge Detection Mode
The NMI edge detection can be operated synchronously or asynchronously to the EIC clock.
In Synchronous Edge Detection mode, the NMI pin is sampled using the EIC clock as defined by the bit CTRLA.CKSEL. The Non-Maskable Interrupt flag (NMIFLAG) is set when the pin and the pin sampler have a different value. In this mode, the EIC clock is required. The Synchronous Edge Detection mode can be used in all Sleep modes except STANDBY.
In Asynchronous Edge Detection mode, the NMI pins directly drive the set of the Non-Maskable Interrupt flag (NMIFLAG). In this mode, the EIC clock is not requested. The Asynchronous Edge Detection Mode can be used in all sleep modes.
| Value | Description |
|---|---|
| 0 | The NMI edge detection is synchronously operated. |
| 1 | The NMI edge detection is asynchronously operated. |
Bit 3 – NMIFILTEN Non-Maskable Interrupt Filter Enable
| Value | Description |
|---|---|
| 0 | NMI filter is disabled. |
| 1 | NMI filter is enabled. |
Bits 2:0 – NMISENSE[2:0] Non-Maskable Interrupt Sense Configuration
These bits define which edge or level the NMI triggers on.
Note: The NMI cannot be triggered based on level, but it is always based on edge.
| Value | Name | Description |
|---|---|---|
| 0x0 | NONE | No detection |
| 0x1 | RISE | Rising-edge detection |
| 0x2 | FALL | Falling-edge detection |
| 0x3 | BOTH | Both-edge detection |
| 0x4 | HIGH | High-level detection |
| 0x5 | LOW | Low-level detection |
| 0x6 - 0x7 | — | Reserved |