25.8.8 Synchronization Busy in COUNT32 mode (CTRLA.MODE=0)

Name: SYNCBUSY
Offset: 0x10
Reset: 0x00000000
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
     GP3GP2GP1GP0 
Access RRRR 
Reset 0000 
Bit 15141312111098 
 COUNTSYNC        
Access R 
Reset 0 
Bit 76543210 
  COMP1COMP0 COUNTFREQCORRENABLESWRST 
Access RRRRRR 
Reset 000000 

Bits 16, 17, 18, 19 – GPn General Purpose n Synchronization Busy Status

ValueDescription
0 Write synchronization for GPn register is complete.
1 Write synchronization for GPn register is ongoing.

Bit 15 – COUNTSYNC Count Read Sync Enable Synchronization Busy Status

ValueDescription
0 Write synchronization for CTRLA.COUNTSYNC bit is complete.
1 Write synchronization for CTRLA.COUNTSYNC bit is ongoing.

Bits 5, 6 – COMPn Compare n Synchronization Busy Status [n = 1..0]

ValueDescription
0 Write synchronization for COMPx register is complete.
1 Write synchronization for COMPx register is ongoing.

Bit 3 – COUNT Count Value Synchronization Busy Status

ValueDescription
0 Read/write synchronization for COUNT register is complete.
1 Read/write synchronization for COUNT register is ongoing.

Bit 2 – FREQCORR Frequency Correction Synchronization Busy Status

ValueDescription
0 Write synchronization for FREQCORR register is complete.
1 Write synchronization for FREQCORR register is ongoing.

Bit 1 – ENABLE Enable Synchronization Busy Status

ValueDescription
0 Write synchronization for CTRLA.ENABLE bit is complete.
1 Write synchronization for CTRLA.ENABLE bit is ongoing.

Bit 0 – SWRST Software Reset Synchronization Busy Status

Note: During a SWRST, access to registers/bits without SWRST are disallowed until SYNCBUSY.SWRST cleared by hardware.
ValueDescription
0 Write synchronization for CTRLA.SWRST bit is complete.
1 Write synchronization for CTRLA.SWRST bit is ongoing.