25.8.1 Control A in COUNT32 mode (CTRLA.MODE=0)

Name: CTRLA
Offset: 0x00
Reset: 0x0000
Property: Enable-Protected, Write-Synchronized

Bit 15141312111098 
 COUNTSYNCGPTRSTBKTRST PRESCALER[3:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 
Bit 76543210 
 MATCHCLR   MODE[1:0]ENABLESWRST 
Access R/WR/WR/WR/WR/W 
Reset 00000 

Bit 15 – COUNTSYNC COUNT Read Synchronization Enable

The COUNT register requires synchronization when reading. Disabling the synchronization prevents reading valid values from the COUNT register.

This bit is not enable-protected.

ValueDescription
0COUNT read synchronization is disabled
1COUNT read synchronization is enabled

Bit 14 – GPTRST GP Registers Reset On Tamper Enable

Only GP registers enabled by the CTRLB.GPnEN bits are affected. This bit can be written only when the peripheral is disabled.

This bit is not synchronized.

Bit 13 – BKTRST BKUP Registers Reset On Tamper Enable

All BKUPn registers are affected. This bit can be written only when the peripheral is disabled.

This bit is not synchronized.

ValueDescription
0BKUPn registers will not reset when a tamper condition occurs.
1BKUPn registers will reset when a tamper condition occurs.

Bits 11:8 – PRESCALER[3:0] Prescaler

These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock (CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off. These bits are not synchronized.
ValueNameDescription
0x0OFFCLK_RTC_CNT = GCLK_RTC/1
0x1DIV1CLK_RTC_CNT = GCLK_RTC/1
0x2DIV2CLK_RTC_CNT = GCLK_RTC/2
0x3DIV4CLK_RTC_CNT = GCLK_RTC/4
0x4DIV8CLK_RTC_CNT = GCLK_RTC/8
0x5DIV16CLK_RTC_CNT = GCLK_RTC/16
0x6DIV32CLK_RTC_CNT = GCLK_RTC/32
0x7DIV64CLK_RTC_CNT = GCLK_RTC/64
0x8DIV128CLK_RTC_CNT = GCLK_RTC/128
0x9DIV256CLK_RTC_CNT = GCLK_RTC/256
0xADIV512CLK_RTC_CNT = GCLK_RTC/512
0xBDIV1024CLK_RTC_CNT = GCLK_RTC/1024
0xC-0xF-Reserved

Bit 7 – MATCHCLR Clear on Match

This bit defines if the counter is cleared or not on a match.

This bit is not synchronized.

ValueDescription
0The counter is not cleared on a Compare/Alarm match
1The counter is cleared on a Compare/Alarm match

Bits 3:2 – MODE[1:0] Operating Mode

This bit group defines the operating mode of the RTC.

This bit is not synchronized.

ValueNameDescription
0x0COUNT32Mode 0: 32-bit counter
0x1COUNT16Mode 1: 16-bit counter
0x2CLOCKMode 2: Clock/calendar
0x3-Reserved

Bit 1 – ENABLE Enable

Due to synchronization, there is a delay writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE reads back immediately, and the Enable bit in the Synchronization Busy register (SYNCBUSY.ENABLE) is set. SYNCBUSY.ENABLE is cleared when the operation is complete.
ValueDescription
0The peripheral is disabled
1The peripheral is enabled

Bit 0 – SWRST Software Reset

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit resets all registers in the RTC (except DBGCTRL) to their initial state, and the RTC is disabled.

Writing a ‘1’ to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write operation is discarded.

Due to synchronization, there is a delay writing CTRLA.SWRST until the Reset is complete. CTRLA.SWRST is cleared when the Reset is complete.
Note: During a SWRST, access to registers/bits without SWRST are disallowed until SYNCBUSY.SWRST is cleared by hardware.
ValueDescription
0There is no Reset operation ongoing
1The Reset operation is ongoing