41.6.2.6 Double Buffering

The Pattern (PATT), Period (PER) and Compare Channels (CCx) registers are all double buffered. Each buffer register has a buffer valid (PATTBUFV, PERBUFV and CCBUFVx) bit in the STATUS register that indicates that the Buffer register contains a valid value that can be copied into the corresponding register.

When the Buffer Valid Flag bit in the STATUS register is ‘1’ and the Lock Update bit in the CTRLB register is set to ‘0’, (writing CTRLBCLR.LUPD to ‘1’), double buffering is enabled: the data from buffer registers is copied into the corresponding register under hardware UPDATE conditions, then, the Buffer Valid flags bit in the STATUS register are automatically cleared by hardware.

Both the registers (PATT/PER/CCx) and corresponding Buffer registers (PATTBUFPERBUF/CCBUFx) are available in the I/O register map, and the double buffering feature is not mandatory. The double buffering is disabled by writing a ‘1’ to CTRLSET.LUPD.

Changing the Period

The counter period can be changed by writing a new Top value to the Period register (PER or CC0, depending on the Waveform Generation mode). Any period update on registers (PER or CCx) is effective after the synchronization delay, regardless of double buffering enabling.

A counter wraparound can occur in any operation mode when up-counting without buffering; see Figure 41-10. COUNT and TOP are continuously compared, so when a new value that is lower than the current COUNT is written to TOP, COUNT wraps before a compare match.

When double buffering is used, the buffer can be written at any time and the counter will still maintain correct operation. The period register is always updated on the update condition, as illustrated in the following figure. This prevents wraparound and the generation of odd waveforms.