Clock Generation (Standard-Mode, Fast-Mode and Fast-Mode Plus)

In I²C Sm, Fm and Fm+ modes, the Host clock (SCL) frequency is determined as described in this section:

The low (T_LOW) and high (T_HIGH) times are determined by the Baud Rate register (BAUD), while the rise (T_RISE) and fall (T_FALL) times are determined by the bus topology. Because of the wired-AND logic of the bus, T_FALL is considered as part of T_LOW. Likewise, T_RISE is in a state between T_LOW and T_HIGH until a high state is detected.

The SCL frequency is given by:

$f_{\mathrm{SCL}}=\frac{1}{T_{\mathrm{LOW}}+T_{\mathrm{HIGH}}+T_{\mathrm{RISE}}}$

When BAUD.BAUDLOW is zero, the BAUD.BAUD value is used to time both SCL high and SCL low. In this case, the following formula gives the SCL frequency:

$f_{\mathrm{SCL}}=\frac{f_{\mathrm{GCLK}}}{{10+2BAUD+}_{}{f}_{\mathrm{GCLK}}\cdot T_{\mathrm{RISE}}}$

When BAUD.BAUDLOW is non-zero, the following formula determines the SCL frequency:

$f_{\mathrm{SCL}}=\frac{f_{\mathrm{GCLK}}}{{10+BAUD+BAUDLOW+}_{}{f}_{\mathrm{GCLK}}\cdot T_{\mathrm{RISE}}}$

The following formulas can determine the SCL T_LOW and T_HIGH times:

$T_{\mathrm{LOW}}=\frac{BAUDLOW+5}{f_{\mathrm{GCLK}}}$

$T_{\mathrm{HIGH}}=\frac{BAUD+5}{f_{\mathrm{GCLK}}}$