37.15.9 PHY Control Register 20
Note: The USB PHY values must be loaded from the CAL OTP area into
the USB PHY registers by software, before enabling the USB, to achieve the specified
accuracy.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | PHY20 |
| Offset: | 0x1520 |
| Reset: | 0x00000080 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| HSSLEW[1:0] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 1 | 0 | |||||||
Bits 7:6 – HSSLEW[1:0] HS Slew Rate
Sets the HS slew rate.
Settings include the lower bits (PHY20.6:7) and the upper bits (PHY24.0).
| Value | Description |
|---|---|
| 111 | Fastest rise/fall time |
| 010 | Middle slew rate |
| 001 | Slowest rise/fall time |
| 000 | Reserved |