11.4.2.3 FUCFG0 - User Configuration Register 0 – WDT Configuration
Name: FUCFG0
- Factory Default: 0x0000_0000
- Value after chip erase: 0x00FF_FFFF
Bits 19-16EWOFFSET[3:0] Early Warning Interrupt Time Offset
These bits determine the number of GCLK_WDT clock cycles between the start of the watchdog time-out period and the generation of the Early Warning interrupt.
| Value | Description |
|---|---|
| 0x0 | 8 GCLK_WDT clock cycles |
| 0x1 | 16 GCLK_WDT clock cycles |
| 0x2 | 32 GCLK_WDT clock cycles |
| 0x3 | 64 GCLK_WDT clock cycles |
| 0x4 | 128 GCLK_WDT clock cycles |
| 0x5 | 256 GCLK_WDT clock cycles |
| 0x6 | 512 GCLK_WDT clock cycles |
| 0x7 | 1024 GCLK_WDT clock cycles |
| 0x8 | 2048 GCLK_WDT clock cycles |
| 0x9 | 4096 GCLK_WDT clock cycles |
| 0xA | 8192 GCLK_WDT clock cycles |
| 0xB | 16384 GCLK_WDT clock cycles |
| 0xC-0xF | Reserved |
Bits 15-12WDT_WIN [3:0] Window Mode Time-Out Period
In window mode, these bits determine the watchdog closed window period as a number of cycles of the 1.024 kHz CLK_WDT_OSC clock.
| Value | Description |
|---|---|
| 0x0 | 8 1kHz clock cycles |
| 0x1 | 16 1kHz clock cycles |
| 0x2 | 32 1kHz clock cycles |
| 0x3 | 64 1kHz clock cycles |
| 0x4 | 128 1kHz clock cycles |
| 0x5 | 256 1kHz clock cycles |
| 0x6 | 512 1kHz clock cycles |
| 0x7 | 1024 1kHz clock cycles |
| 0x8 | 2048 1kHz clock cycles |
| 0x9 | 4096 1kHz clock cycles |
| 0xA | 8192 1kHz clock cycles |
| 0xB | 16384 1kHz clock cycles |
| 0xC-0xF | Reserved |
Bits 11-8 – PER[3:0] Time-Out Period
These bits determine the watchdog time-out period as a number of 1.024 kHz CLK_WDT_OSC clock cycles. In window mode operation, these bits define the open window period.
| Value | Description |
|---|---|
| 0x0 | 8 1kHz clock cycles |
| 0x1 | 16 1kHz clock cycles |
| 0x2 | 32 1kHz clock cycles |
| 0x3 | 64 1kHz clock cycles |
| 0x4 | 128 1kHz clock cycles |
| 0x5 | 256 1kHz clock cycles |
| 0x6 | 512 1kHz clock cycles |
| 0x7 | 1024 1kHz clock cycles |
| 0x8 | 2048 1kHz clock cycles |
| 0x9 | 4096 1kHz clock cycles |
| 0xA | 8192 1kHz clock cycles |
| 0xB | 16384 1kHz clock cycles |
| 0xC-0xF | Reserved |
Bit 7 – ALWAYSON Always-On
This bit allows the WDT to run continuously.
| Value | Description |
|---|---|
| 0 | The WDT is enabled and disabled through the ENABLE bit. |
| 1 | The WDT is enabled and can only be disabled by a Power-on Reset (POR). |
Bit 6 – RUNSTDBY Run in Standby
This bit controls the behavior of the watchdog during Standby Sleep mode.
| Value | Description |
|---|---|
| 0 | The WDT is disabled during Standby sleep |
| 1 | The WDT is enabled continues to operate during Standby sleep |
Bit 2 – WEN Watchdog Timer Window Mode Enable
This bit enables window mode.
| Value | Description |
|---|---|
| 0 | Window mode is disabled |
| 1 | Window mode is enabled |
Bit 1 – ENABLE Enable
This bit enables or disables the WDT.
| Value | Description |
|---|---|
| 0 | The WDT is disabled. |
| 1 | The WDT is enabled. |