35.8.7.1 Control A

Table 35-63. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected

Bit 3130292827262524 
  LOWTOUTINACTOUT[1:0]SCLSM SPEED[1:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 2322212019181716 
 SEXTTOENMEXTTOENSDAHOLD[1:0]  SMBUSENPINOUT 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 15141312111098 
     SLEWRATE[1:0]FILTSEL[1:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
 RUNSTDBY  MODE[2:0]ENABLESWRST 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bit 30 – LOWTOUT SCL Low Time-Out Enable

This bit enables the SCL low time-out. If SCL is held low for 25 ms-35 ms, the Host will release its clock hold, if enabled, and complete the current transaction. A stop condition will automatically be transmitted.

INTFLAG.SB or INTFLAG.MB will be set as normal, but the clock hold will be released. The STATUS.LOWTOUT and STATUS.BUSERR status bits will be set.

This bit is not synchronized.

ValueDescription
0Time-out disabled.
1Time-out enabled.

Bits 29:28 – INACTOUT[1:0] Inactive Time-Out

If the inactive bus time-out is enabled and the bus is inactive for longer than the time-out setting, the bus state logic will be set to idle. An inactive bus arises when either an I2C host or client is holding the SCL low.

Enabling this option is necessary for SMBus compatibility, but can also be used in a non-SMBus set-up.

Calculated time-out periods are based on a 100 kHz baud rate.

These bits are not synchronized.

ValueNameDescription
0x0DISDisabled
0x155US5-6 SCL cycle time-out (50-60µs)
0x2105US10-11 SCL cycle time-out (100-110µs)
0x3205US20-21 SCL cycle time-out (200-210µs)

Bits 25:24 – SPEED[1:0] Transfer Speed

These bits define bus speed.

These bits are not synchronized.

ValueDescription
0x0Standard-mode (Sm) up to 100 kHz and Fast-mode (Fm) up to 400 kHz
0x1Fast-mode Plus (Fm+) up to 1 MHz
0x2High-speed mode (Hs-mode) up to 3.4 MHz
0x3Reserved

Bit 23 – SEXTTOEN Client SCL Low Extend Time-Out Enable

This bit enables the client SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the host will release its clock hold if enabled, and complete the current transaction. A STOP will automatically be transmitted.

SB or MB will be set as normal, but CLKHOLD will be released. The MEXTTOUT and BUSERR status bits will be set.

This bit is not synchronized.

ValueDescription
0Time-out disabled
1Time-out enabled

Bit 22 – MEXTTOEN Host SCL Low Extend Time-Out Enable

This bit enables the host SCL low extend time-out. If SCL is cumulatively held low for greater than 10ms from START-to-ACK, ACK-to-ACK, or ACK-to-STOP the host will release its clock hold if enabled, and complete the current transaction. A STOP will automatically be transmitted.

SB or MB will be set as normal, but CLKHOLD will be released. The MEXTTOUT and BUSERR status bits will be set.

This bit is not synchronized.

ValueDescription
0Time-out disabled
1Time-out enabled

Bits 21:20 – SDAHOLD[1:0] SDA Hold Time

These bits define the SDA hold time with respect to the negative edge of SCL.

These bits are not synchronized.

ValueNameDescription
0x0DISDisabled
0x175NS50-100ns hold time
0x2450NS300-600ns hold time
0x3600NS400-800ns hold time

Bit 17 – SMBUSEN SMBus Input Buffer Enable

This bit enables SMBus-compatible I/O logic level.

This bit is not synchronized.

ValueDescription
0SMBus input buffer is disabled.
1SMBus input buffer is enabled.

Bit 16 – PINOUT Pin Usage

This bit set the pin usage to either two- or four-wire operation:

This bit is not synchronized.

ValueDescription
04-wire operation disabled.
14-wire operation enabled.

Bits 11:10 – SLEWRATE[1:0] Slew Rate Enable

This bit enables the I/O pins slew rate control.

This bit is not synchronized.

ValueNameDescription
0x0SMStandard Mode
0x1FMFast Mode
0x2FMPFast Mode Plus
0x3HSHigh-speed Mode

Bits 9:8 – FILTSEL[1:0] Input Filter Selection

These bits define filter length applied to the input signals.

These bits are not synchronized.

ValueNameDescription
0x0DISDisabled
0x1-Reserved
0x250EMinimum 50ns filter (SDA even mode)
0x310Minimum 10ns filter

Bit 7 – RUNSTDBY Run in Standby

This bit defines the functionality in standby sleep mode.

This bit is not synchronized.

ValueDescription
0GCLK_SERCOMx_CORE is disabled and the I2C host will not operate in standby sleep mode.
1GCLK_SERCOMx_CORE is enabled in all sleep modes.

Bits 4:2 – MODE[2:0] Operating Mode

These bits must be written to 0x5 to select the I2C host serial communication interface of the SERCOM.

These bits are not synchronized.

Bit 1 – ENABLE Enable

Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately and the Synchronization Enable Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.

This bit is not enable-protected.

ValueDescription
0The peripheral is disabled or being disabled.
1The peripheral is enabled.

Bit 0 – SWRST Software Reset

Writing '0' to this bit has no effect.

Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled.

Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in a bus error. Reading any register will return the reset value of the register.

Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.

This bit is not enable-protected.

Note:
  1. When the CTRLA.SWRST is written, the user should poll the SYNCB.SWRST bit to know when the reset operation is complete.
  2. During a SWRST, access to registers/bits without SWRST are disallowed until the SYNCBUSY.SWRST is cleared by the hardware.
ValueDescription
0There is no reset operation ongoing.
1The reset operation is ongoing.