35.8.7.2 Control B

Table 35-64. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: CTRLB
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
 FIFOCLR[1:0]   ACKACTCMD[1:0] 
Access R/WR/WR/WWW 
Reset 00000 
Bit 15141312111098 
       QCENSMEN 
Access R/WR/W 
Reset 00 
Bit 76543210 
          
Access  
Reset  

Bits 23:22 – FIFOCLR[1:0] FIFO Clear

When these bits are set, the corresponding FIFO will be cleared. The bits will automatically clear when SYNCBUSY.SYSOP = 0.

These bits are not enable-protected.

FIFOCLR[1:0]NameDescription
0x0NONENo action
0x1TXFIFOClear TX FIFO
0x2RXFIFOClear RX FIFO
0x3BOTHClear both TX/RX FIFO

Bit 18 – ACKACT Acknowledge Action

This bit defines the I2C host's acknowledge behavior after a data byte is received from the I2C client. The acknowledge action is executed when a command is written to CTRLB.CMD, or if Smart mode is enabled (CTRLB.SMEN is written to one), when DATA.DATA is read.

This bit is not enable-protected.

This bit is not write-synchronized.

ValueDescription
0Send ACK.
1Send NACK.

Bits 17:16 – CMD[1:0] Command

Writing these bits triggers a host operation as described below. The CMD bits are strobe bits, and always read as zero. The acknowledge action is only valid in Host Read mode. In Host Write mode, a command will only result in a repeated Start or Stop condition. The CTRLB.ACKACT bit and the CMD bits can be written at the same time, and then the acknowledge action will be updated before the command is triggered.

Commands can only be issued when either the Client on Bus Interrupt flag (INTFLAG.SB) or Host on Bus Interrupt flag (INTFLAG.MB) is '1'.

If CMD 0x1 is issued, a repeated start will be issued followed by the transmission of the current address in ADDR.ADDR. If another address is desired, ADDR.ADDR must be written instead of the CMD bits. This will trigger a repeated start followed by transmission of the new address.

Issuing a command will set the System Operation bit in the Synchronization Busy register (SYNCBUSY.SYSOP).

Table 35-65. Command Description
CMD[1:0]DirectionAction
0x0X(No action)
0x1XExecute acknowledge action succeeded by repeated Start
0x20 (Write)No operation
1 (Read)Execute acknowledge action succeeded by a byte read operation
0x3XExecute acknowledge action succeeded by issuing a Stop condition

These bits are not enable-protected.

Bit 9 – QCEN Quick Command Enable

This bit is not write-synchronized.

ValueDescription
0Quick Command is disabled.
1Quick Command is enabled.

Bit 8 – SMEN Smart Mode Enable

When Smart mode is enabled, acknowledge action is sent when DATA.DATA is read.

This bit is not write-synchronized.

ValueDescription
0Smart mode is disabled.
1Smart mode is enabled.