35.8.7.3 Control C

Table 35-66. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: CTRLC
Offset: 0x08
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected

Bit 3130292827262524 
 TXTRHOLD[1:0]RXTRHOLD[1:0]FIFOEN  DATA32B 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
          
Access  
Reset  

Bits 31:30 – TXTRHOLD[1:0] Transmit FIFO Threshold

These bits define the threshold for generating the Data Register Empty interrupt and DMA TX trigger.

TXTRHOLDNameDescription
0DEFAULTInterrupt and DMA triggers can be generated as long as the FIFO is not full.
1HALFInterrupt and DMA triggers are generated when half FIFO space is free.
2EMPTYInterrupt and DMA triggers are generated when the FIFO is empty.
3-Reserved

Bits 29:28 – RXTRHOLD[1:0] Receive FIFO Threshold

These bits define the threshold for generating the RX Complete interrupt and DMA RX trigger.

RXTRHOLDNameDescription
0DEFAULTInterrupt and DMA triggers can be generated when a DATA is present in the FIFO.
1HALFInterrupt and DMA triggers can be generated only when the FIFO is half-full.
2FULLInterrupt and DMA triggers can be generated only when the FIFO is full.
3-Reserved

Bit 27 – FIFOEN FIFO Enable

This bit enables the FIFO operation.

ValueDescription
0FIFO operation is disabled
1FIFO operation is enabled

Bit 24 – DATA32B Data 32 Bit

This bit enables 32-bit data writes and reads to/from the DATA register.

ValueDescription
0Data transactions to/from DATA are 8-bit in size
1Data transactions to/from DATA are 32-bit in size