44.7.15 Counter Value
Note: Prior to any read access, this
register must be synchronized by user by writing the according TCC Command value to
the Control B Set register (CTRLBSET.CMD(CTRLBSET<7:5>)=READSYNC).
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | COUNT |
| Offset: | 0x34 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection, Write-Synchronized, Read-Synchronized |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| COUNT[31:24] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| COUNT[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| COUNT[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| COUNT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:0 – COUNT[31:0] Counter Value
These bits hold the value of the Counter register. When dithering is used, some LSBs of the counter cannot be used for counting and are read to 0. These bits are used for dithering. The number of LSBs used for dithering depends on the dithering resolution set by the CTRLA.RESOLUTION bits (CTRLA <6:5>).
Note: This bit field occupies the MSB
of the register, [31:m]. m is dependent on the Resolution bit in the Control A
register (CTRLA.RESOLUTION(CTRLA <6:5>)):
| CTRLA.RESOLUTION | Bits [31:m] |
|---|---|
| 0x0 - NONE | 31:0 (default) |
| 0x1 - DITH4 | 31:4 |
| 0x2 - DITH5 | 31:5 |
| 0x3 - DITH6 | 31:6 |