44.7.22 Channel y Compare/Capture Buffer Value
Note: This register must be written with 32 bit accesses only (no 8 or 16 bit writes).
CCBUFy is copied into CCy at TCC update time.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CCBUFy |
| Offset: | 0x70 + y*0x04 [y=0..7] |
| Reset: | 0x00000000 |
| Property: | Write-Synchronized, Read-Synchronized |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CCBUF[25:18] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CCBUF[17:10] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CCBUF[9:2] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CCBUF[1:0] | DITHERBUF[5:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:6 – CCBUF[25:0] Channel y Compare/Capture Buffer Value
These bits hold the value of the Channel y Compare/Capture Buffer Value register. The register serves as the buffer for the associated compare or capture registers (CCy). Accessing this register using the CPU or DMA will affect the corresponding STATUS.CCBUFVy status bit.
Note:
- This bit field occupies
the MSB of the register, [31:m]. m is dependent on the Resolution bit in
the Control A register (CTRLA.RESOLUTION(CTRLA <6:5>)):
CTRLA.RESOLUTION(CTRLA <6:5>) Bits [31:m] 0x0 - NONE 31:0 0x1 - DITH4 31:4 0x2 - DITH5 31:5 0x3 - DITH6 31:6 (depicted)
Bits 5:0 – DITHERBUF[5:0] Dithering Buffer Cycle Number
Note: This bit field consists of the n
LSB of the register. n is dependent on the value of the Resolution bits in the
Control A register (CTRLA.RESOLUTION(CTRLA <6:5>)):
| CTRLA.RESOLUTION(CTRLA <6:5>) | Bits [n:0] |
|---|---|
| 0x0 - NONE | - |
| 0x1 - DITH4 | 3:0 |
| 0x2 - DITH5 | 4:0 |
| 0x3 - DITH6 | 5:0 (depicted) |