44.7.20 Pattern Buffer
Note: This register must be written with 16 bit accesses only (no 8 bit writes).
Table 44-29. Register Bit Attribute
Legend| Symbol | Description | Symbol | Description | Symbol | Description |
|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | PATTBUF |
| Offset: | 0x64 |
| Reset: | 0x0000 |
| Property: | Write-Synchronized,
Read-Synchronized |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | PGVB[7:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | PGEB[7:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:8 – PGVB[7:0] Pattern Generation
Output Value Buffer
This register is the
buffer for the PGV register. If double buffering is used, valid content in this
register is copied to the PGV register on an UPDATE condition.
Bits 7:0 – PGEB[7:0] Pattern Generation
Output Enable Buffer
This register is the
buffer of the PGE register. If double buffering is used, valid content in this
register is copied into the PGE register at an UPDATE
condition.
