44.7.19 Compare/Capture Channel y

The CCy register represents the 32-bit value. The register has two functions, depending of the mode of operation.

For capture operation, this register represents the second buffer level and access point for the CPU and DMA.

For compare operation, this register is continuously compared to the counter value. Normally, the output form the comparator is then used for generating waveforms.

CCy register is updated with the buffer value from their corresponding CCBUFy register when an UPDATE condition occurs.

In addition, in match frequency operation, the CC0 register controls the counter period.

Table 44-28. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: CCy
Offset: 0x44 + y*0x04 [y=0..7]
Reset: 0x00000000
Property: Write-Synchronized, Read-Synchronized

Bit 3130292827262524 
 CC[25:18] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 CC[17:10] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 CC[9:2] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 CC[1:0]DITHER[5:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 31:6 – CC[25:0] Channel y Compare/Capture Value

These bits hold the value of the Channel y compare/capture register.

Note:
  1. This bit field occupies the MSB of the register, [31:m]. m is dependent on the Resolution bit in the Control A register (CTRLA.RESOLUTION(CTRLA <6:5>)):
    CTRLA.RESOLUTIONBits [31:m]
    0x0 - NONE31:0
    0x1 - DITH431:4
    0x2 - DITH531:5
    0x3 - DITH631:6 (depicted)

Bits 5:0 – DITHER[5:0] Dithering Cycle Number

These bits hold the number of extra cycles that are added on the PWM pulse width every 64 PWM frames.
Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the Control A register (CTRLA.RESOLUTION(CTRLA <6:5>)):
CTRLA.RESOLUTIONBits [n:0]
0x0 - NONE-
0x1 - DITH43:0
0x2 - DITH54:0
0x3 - DITH65:0 (depicted)