44.7.19 Compare/Capture Channel y
The CCy register represents the 32-bit value. The register has two functions, depending of the mode of operation.
For capture operation, this register represents the second buffer level and access point for the CPU and DMA.
For compare operation, this register is continuously compared to the counter value. Normally, the output form the comparator is then used for generating waveforms.
CCy register is updated with the buffer value from their corresponding CCBUFy register when an UPDATE condition occurs.
In addition, in match frequency operation, the CC0 register controls the counter period.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CCy |
| Offset: | 0x44 + y*0x04 [y=0..7] |
| Reset: | 0x00000000 |
| Property: | Write-Synchronized, Read-Synchronized |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CC[25:18] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CC[17:10] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CC[9:2] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CC[1:0] | DITHER[5:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:6 – CC[25:0] Channel y Compare/Capture Value
These bits hold the value of the Channel y compare/capture register.
- This bit field occupies
the MSB of the register, [31:m]. m is dependent on the Resolution bit in
the Control A register (CTRLA.RESOLUTION(CTRLA <6:5>)):
CTRLA.RESOLUTION Bits [31:m] 0x0 - NONE 31:0 0x1 - DITH4 31:4 0x2 - DITH5 31:5 0x3 - DITH6 31:6 (depicted)
Bits 5:0 – DITHER[5:0] Dithering Cycle Number
| CTRLA.RESOLUTION | Bits [n:0] |
|---|---|
| 0x0 - NONE | - |
| 0x1 - DITH4 | 3:0 |
| 0x2 - DITH5 | 4:0 |
| 0x3 - DITH6 | 5:0 (depicted) |