44.7.10 Event Control
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | EVCTRL |
| Offset: | 0x20 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| MCEO7 | MCEO6 | MCEO5 | MCEO4 | MCEO3 | MCEO2 | MCEO1 | MCEO0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| MCEI7 | MCEI6 | MCEI5 | MCEI4 | MCEI3 | MCEI2 | MCEI1 | MCEI0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TCEI1 | TCEI0 | TCINV1 | TCINV0 | CNTEO | TRGEO | OVFEO | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CNTSEL[1:0] | EVACT1[2:0] | EVACT0[2:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 24, 25, 26, 27, 28, 29, 30, 31 – MCEOy Match or Capture Channel y Event Output Enable
These bits control if the Match/capture event on channel y is enabled and will be generated for every match or capture.
| Value | Description |
|---|---|
| 0 | Match/capture y event is disabled and will not be generated. |
| 1 | Match/capture y event is enabled and will be generated for every compare/capture on channel y. |
Bits 16, 17, 18, 19, 20, 21, 22, 23 – MCEIy Fault A/B or Capture Channel y Event Input Enable
These bits indicate if the Match/capture y incoming event is enabled
These bits are used to enable Fault A/B or capture input events to the CCy channel of TCCC.
| Value | Description |
|---|---|
| 0 | Incoming events are disabled. |
| 1 | Incoming events are enabled. |
Bits 14, 15 – TCEIn Timer/Counter Event Input n Enable
This bit is used to enable input event n to the TCC.
| Value | Description |
|---|---|
| 0 | Incoming event n is disabled. |
| 1 | Incoming event n is enabled. |
Bits 12, 13 – TCINVn Timer/Counter Event n Invert Enable
This bit inverts the event n input.
| Value | Description |
|---|---|
| 0 | Input event source n is not inverted. |
| 1 | Input event source n is inverted. |
Bit 10 – CNTEO Timer/Counter Event Output Enable
This bit is used to enable the counter cycle event. When enabled, an event will be generated on begin or end of counter cycle depending of on EVCTRL.CNTSEL(EVCTRL<7:6>) settings.
| Value | Description |
|---|---|
| 0 | Counter cycle output event is disabled and will not be generated. |
| 1 | Counter cycle output event is enabled and will be generated depending on EVCTRL.CNTSEL(EVCTRL<7:6>) value. |
Bit 9 – TRGEO Retrigger Event Output Enable
This bit is used to enable the counter retrigger event. When enabled, an event will be generated when the counter retriggers operation.
| Value | Description |
|---|---|
| 0 | Counter retrigger event is disabled and will not be generated. |
| 1 | Counter retrigger event is enabled and will be generated for every counter retrigger. |
Bit 8 – OVFEO Overflow/Underflow Event Output Enable
This bit is used to enable the overflow/underflow event. When enabled an event will be generated when the counter reaches the TOP or the ZERO value.
| Value | Description |
|---|---|
| 0 | Overflow/underflow counter event is disabled and will not be generated. |
| 1 | Overflow/underflow counter event is enabled and will be generated for every counter overflow/underflow. |
Bits 7:6 – CNTSEL[1:0] Timer/Counter Interrupt and Event Output Selection
These bits define on which part of the counter cycle the counter event output is generated.
| Value | Name | Description |
|---|---|---|
| 0x0 | START | An interrupt/event is generated at begin of each counter cycle |
| 0x1 | END | An interrupt/event is generated at end of each counter cycle |
| 0x2 | - | Reserved |
| 0x3 | BOUNDARY | An interrupt/event is generated at begin of first counter cycle, and end of last counter cycle. |
Bits 5:3 – EVACT1[2:0] Timer/Counter Event Input 1 Action
These bits define the action the TCC will perform on TCE1 event input.
| Value | Name | Description |
|---|---|---|
| 0x0 | OFF | Event action disabled. |
| 0x1 | RETRIGGER | Start, restart or re-trigger TCC on event |
| 0x2 | DIR (asynch) | Direction control |
| 0x3 | STOP | Stop TCC on event |
| 0x4 | DEC | Decrement TCC on event |
| 0x5 | - | Reserved |
| 0x6 | PWP | Period captured into CC1 Pulse Width on CC0 |
| 0x7 | FAULT | Non-recoverable Fault |
Bits 2:0 – EVACT0[2:0] Timer/Counter Event Input 0 Action
These bits define the action the TCC will perform on TCE0 event input 0.
| Value | Name | Description |
|---|---|---|
| 0x0 | OFF | Event action disabled. |
| 0x1 | RETRIGGER | Start, restart or re-trigger TCC on event |
| 0x2 | COUNTEV | Count on event. |
| 0x3 | START | Start TCC on event |
| 0x4 | INC | Increment TCC on EVENT |
| 0x5 | COUNT (async) | Count on active state of asynchronous event |
| 0x6 | STAMP | Capture overflow times (Max value) |
| 0x7 | FAULT | Non-recoverable Fault |