44.7.7 Waveform Extension Control

Table 44-16. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: WEXCTRL
Offset: 0x14
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected

Bit 3130292827262524 
 DTHS[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 DTLS[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
     DTIEN3DTIEN2DTIEN1DTIEN0 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
       OTMX[1:0] 
Access R/WR/W 
Reset 00 

Bits 31:24 – DTHS[7:0] Dead-Time High Side Outputs Value

This register holds the number of GCLK_TCCx clock cycles for the dead-time high side.

Bits 23:16 – DTLS[7:0] Dead-time Low Side Outputs Value

This register holds the number of GCLK_TCCx clock cycles for the dead-time low side.

Bits 8, 9, 10, 11 – DTIEN Dead-time Insertion Generator y Enable

Setting any of these bits enables the dead-time insertion generator for the corresponding output matrix. This will override the output matrix [y] and [y+WO_NUM/2], with the low side and high side waveform respectively.

ValueDescription
0No dead-time insertion override.
1Dead time insertion override on signal outputs[y] and [y+WO_NUM/2], from matrix outputs[y] signal.

Bits 1:0 – OTMX[1:0] Output Matrix

These bits define the matrix routing of the TCC waveform generation outputs to the port pins, according to Waveform Extension.