31.3.13.4 Usage Model for Fault Capture
When FFLTCTRL.FLTMD selects Fault Capture Mode, logic captures ECC/Parity status information. Capture only occurs when the INTFLAG.FLTCAP = 0, and never when it is ONE. In other words, once a fault capture has occurred any additional faults are ignored until INTFLAG.FLTCAP is cleared. Capture occurs for a read only on the detection of a fault which also cause logic to set INTFLAG.FLTCAP = 1. Capture occurs for each flash write but the INTFLAG.FLTCAP bit remains ZERO. This allows write ECC logic to be checked without interfering with fault events causing a read capture. Note that the write ECC/Parity logic is incapable of generating an error interrupt.
If there are simultaneous read errors, the event associated with AHB0 is captured. If AHB0 is not involved, then the event associated with Panel 1 is captured and the event associated with Panel 2 is dropped. If the simultaneous capture is between a read and a write, the read event is captured.
Only fields pertinent to the ECC/Parity Mode are valid. FFLTCAP.FLTADR always captures the address at which the fault occurs (or for any write). FFLTSYN.CTLSTAT and FFLTSYN.CERR are valid only for Dynamic ECC mode. If the access uses ECC then control logic updates the FFLTSYN fields SECSYN, DEDSYN, SERR, and DERR, plus all fields in FFLTPAR. If the access uses Simple Parity then control logic updates FFLTSYN.PERR.