31.3.13.1 Flash Panel ECC Organization

The following table shows the ECC Calculation Vector bit order with respect to flash data bits and parity bits. The first column is the ECC Calculation Vector. The next two columns map the Read/Write Data and ECC Parity bits to the Calculation Vector. V[n] defines the bit which is selected by FFLT*PTR, so n=FFLT*PTR.

Table 31-22. Flash ECC Vector
Vector BitsData BitsECC Parity Bits
V[n]D[n]EP[n]
0-0
1-1
2-2
30-
4-3
7:53:1-
8-4
15:910:4-
16-5
31:1725:11-
32-6
63:3356:26-
64-7
127:65119:57-
128-8
136:129127:120-
255:137246:128-
256-9
265:257255:247-

The following table shows the ECCCTL and CTL field decode. The CTL field is stored in Flash and the fault logic can inject errors into it based on FFLTCTRL.CTLFLT.

Table 31-23. ECC Control Bits
Error Correction ModeECCCTL[1:0]Write Value CTL[2:0]Read Values CTL[2:0]Operation
Bypass Mode2’b113’b000Don’t CareQuad Write w/ ECC Read w/o ECC Check
3’b111Don’t CareSingle Write w/ Parity Read w/o Parity Check
Dynamic Mode w/o Bus Error2’b103’b000

3’b000

3’b001

3’b010

3’b100

Quad Write w/ ECC

Read w/ ECC but w/o DED bus error DERR valid

3’b111

3’b111

3’b110

3’b101

3’b011

Single Write w/ Parity Read w/o Parity buserror DERR valid
Dynamic Mode2’b013’b000

3’b000

3’b001

3’b010

3’b100

Quad Write w/ ECC Read w/ ECC
3’b111

3’b111

3’b110

3’b101

3’b011

Single Write w/ Parity Read w/ Parity
ECC Mode2’b003’b000Don’t CareQuad Write w/ ECC Read w/ ECC
N/AN/ASingle Write is not available in this mode. All reads use ECC.
Note: If switching modes, Single Writes in Bypass or Dynamic cause SEC and DED errors in ECC mode. It is highly recommend to select and use only one Error Correction Mode.