25.7.8.11 CRC Calculations

The CRC engine is a parallel CRC circuit.

The engine implements a programmable internal feed-back LSFR in parallel fashion. Since internal feedback is provided, zero padding at the end of a data block is not required to obtain the final CRC. The engine operates either on 8-bits, 16-bits, or 32-bits of data per clock cycle and supports either 16-bit or 32-bit polynomials. Any combination of 8/16/32 bit word length and 16/32 bit polynomial are supported.

Data entering the block will be reordered such that the CRC checksum calculated for a block is the same regardless of read address mode (byte mode, half-word mode, or word mode). This reordering is completely transparent to software and is independent from the BYTORD setting chosen by the user. Because the system is little endian, in order to get the same CRC result, read halfwords will be byte swapped, and read words will have bytes in reverse order.