42.6.6.1 Interleaving Samples for Higher Sample Rate
The interleaving of ADC CORES provides a method of increasing the sampling rates of the ADC. The interleaving process involves two or more ADC cores (determined by CTRLC.CORINTERLEAVED[1:0]) with a given same analog input signal being sampled at different times by the interleaved ADCs. Only one input channel per each ADC module must be configured for the interleaving trigger source. The remaining input channels must be configured for NOP triggers. The trigger mode must be EVSYS rising edge only, not level.
| Number of Interleaved ADCs Used | Interleaved ADC Modules | CTRLC. CORINTERLEAVED | 12-bit Msps (Max.) [Min Trigger rate] | 10-bit Msps (Max.) [Min Trigger rate] | 8-bit Msps (Max.) [Min Trigger rate] | 6-bit Msps (Max.) [Min Trigger rate] |
|---|---|---|---|---|---|---|
| 2 | 1,2 | =0b001 | 1 / (8 * TAD) [8 TAD] | 1/ (7 * TAD) [7 TAD] | 1/ (6 * TAD) [6 TAD] | 1 / (4.5 * TAD) [4.5 TAD] |
| 0,1 | =0b100 | 1 / (10 * TAD) [10 TAD] | 1/ (8.5 * TAD) [8.5 TAD] | 1/ (7,5 * TAD) [7.5 TAD] | 1 / (6.5 * TAD) [6.5 TAD] | |
| 3 | 1,2,3 | =0b010 | 1 / (5.5 * TAD) [5.5 TAD] | 1/ (5 * TAD) [5 TAD] | 1 / (4 *TAD) [4 TAD] | 1 / (3 * TAD) [3 TAD] |
| 0,1,2 | =0b101 | 1 / (6.5 * TAD) [6.5 TAD] | 1 / (6 * TAD) [6 TAD] | 1 / (5 * TAD) [5 TAD] | 1 / (4.5 * TAD) [4.5 TAD] | |
| 4 | 0,1,2,3 | =0b011 | 1 / (5 * TAD) [5 TAD] | 1 / (4.5 * TAD) [4.5 TAD] | 1 / (4 *TAD) [4 TAD] | 1 / (3.5 * TAD) [3.5 TAD] |
Minimum CORCTRLn.SAMC sample time values for 12/10/8/6-bit Resolution:
- ADC0: CORCTRL0.SAMC = 4 (i.e., = 6 TAD sample time)
- ADC1: CORCTRL1.SAMC = 1 (i.e., = 3 TAD sample time)
- ADC2: CORCTRL2.SAMC = 1 (i.e., = 3 TAD sample time)
- ADC3: CORCTRL3.SAMC = 1 (i.e., = 3 TAD sample time)
- Conversion Time = (#bits Resolution + 1)
- The table above assumes event trigger source GCLK is 2x GCLK_ADC. This allows 0.5 TAD increments. If not, and trigger source GCLK is equal to GCLK_ADC then maximum throughput rate and minimum trigger rate must be rounded up to next whole integer TAD value.
- TAD is the ADC_CLOCK period time
in nano seconds (see ADC electrical specifications).
ADCn TAD = GLK_ADC / [(CTRLD.CTLCKDIV +1) * (CONFIG[n].CORCTRL.ADCDIV * 2)]
- Assumes EVSYS trigger peripheral clock = (2 / TAD) = (2 * GCLK_ADC).
- Must use the same analog input AINx on ADCn modules being interleaved.
- These bits are Enabled Protected (writes are ignored when CTRLA.ENABLE = 1 and will return a bus error).
- ADC0, due to the higher number of analog inputs it services have a higher minimum CONFIG[n].CORCTRL.SAMC sample time that the user must consider since the slowest ADC affects the maximum combination of ADC interleaved throughput rate. ADC 1, 2, and 3 have an identical CONFIG[n].CORCTRL.SAMC minimum sample time.
- In interleaved mode, for the user selected active interleaved ADC modules, the sample or conversion sequence occurs from lowest-to-highest ADC modules (natural order priority ADC0 -> ADC1 -> ADC2 -> ADC3). The trigger event, although it must be common to all the interleaved ADC modules, is sequenced by the ADC hardware singularly, one at a time, to each interleaved ADC group according to the natural priority of the ADC modules.
- In interleaved mode for fastest
conversion speeds, the trigger clock source timing resolution should be
TAD/2.
For example, ADC triggered by TCC timer.
ADC TAD = 75 MHz, (13.333 ns), TCC timer increment = 150 MHz, (6.667 ns)